RE: [sv-cc] Mantis 1570: integer and time types

Ralph, I agree that this works -- i.e., is sufficient.
 
But I was wondering if you had considered adding the integer
and time types to the mapping table in F.6.4.  To me, that
would seem more consistent with the general flow.
 
Regards,
Jim

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James H. Vellenga                            978-262-6381
Engineering Director                   (FAX) 978-262-6636
Cadence Design Systems, Inc.         vellenga@cadence.com
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information."
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________________________________

	From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf
Of Duncan, Ralph
	Sent: Thursday, August 24, 2006 1:41 PM
	To: sv-cc@verilog.org
	Subject: [sv-cc] Mantis 1570: integer and time types
	
	

	New Mantis item 1570:

	 

	Currently, LRM section F.6.3 states that SV types 'integer' and
'time' are legal as base types
	for enumeration types and are represented as 4-state packed
types in canonical form.

	 

	However, there is no explicit mention of whether 'integer' and
'time' are legal DPI import formal

	types as 

	. stand-alone types

	. element types of arrays,

	. struct field types, etc.

	 

	The proposal would clarify things by adding a one sentence
bullet to F.6.3 saying that 'integer' and 'time'

	are represented on the C side as 4-state packed arrays with 32
and 64-bit lengths, respectively.

	 

	Thanks for considering the proposal; please let everyone know if
you have comments, concerns or 
	related issues.

	 

	Ralph

	 

	 

	Ralph Duncan

	Mentor Graphics

	San Jose, CA