Although Verilog did define scalar differently than in other use, it retained the meaning of a contrast to vector. And it actually has a logic to it. If you visualize a vector as a line, as in elementary physics or in elementary computer graphics, then a scalar is a point. Apply that to computer storage, and a vector is a string (line) of bits, whereas a scalar is a single bit. Shalom ________________________________ From: Ralph Duncan [mailto:RDuncan@CloudShield.com] Sent: Monday, June 04, 2007 6:51 PM To: Bresticker, Shalom; Stickley, John; SV-CC Subject: RE: [sv-cc] 'Scalar' term for SV function results, etc. Shalom, 1. The intent certainly is to distinguish a single value from aggregate/composite values. 2. Despite the original, non-vector meaning, common use of 'scalar' does seem to mean single value: http://en.wikipedia.org/wiki/Scalar_%28computing%29 3. The SV definition of 'scalar' as 1-bit wide is in 6.8. 4. String appears to be included because we are indicating the pointer to the string, rather than the string, itself. 5. 'Singular' seems reasonable; the only obvious alternative is to spell out that it's not an aggregate or composite (e.g., array, vector, structure). Does anyone some memorable and snappy alternative? Ralph -----Original Message----- From: owner-sv-cc@server.eda.org [mailto:owner-sv-cc@server.eda.org]On Behalf Of Bresticker, Shalom Sent: Monday, June 04, 2007 7:09 AM To: Stickley, John; SV-CC Subject: RE: [sv-cc] import/export function result types In SV, a scalar is a one-bit value. "Singular" would be closer. Shalom ________________________________ From: Stickley, John [mailto:john_stickley@mentor.com] Sent: Monday, June 04, 2007 5:03 PM To: Bresticker, Shalom; SV-CC Subject: RE: [sv-cc] import/export function result types A possible replacement for this term is "scalar values". That is the term used in VHDL and is probably less vague. -- johnS -----Original Message----- From: owner-sv-cc@server.eda.org on behalf of Bresticker, Shalom Sent: Mon 6/4/2007 5:30 AM To: SV-CC Subject: [sv-cc] import/export function result types Hi, In Draft 3, 34.2.2 says, A rich subset of SystemVerilog data types is allowed for formal arguments of import and export functions, although with some restrictions and with some notational extensions. Function result types are restricted to small values, however (see 34.5.5). and 34.5.5 has a similar statement and details the exact restrictions. However the phrase "small values" sounds strange. In what way are real, longint, and string 'small', for example? Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6852 +972 54 721-1033 -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jun 5 01:03:45 2007
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