Hi Lisa, My comments below. Also summary for my perceived AIs. Thx. -Bassam. From: Lisa Piper [mailto:piper@cadence.com] Sent: Thursday, April 17, 2008 4:23 PM To: Korchemny, Dmitry; bassam.tabbara@synopsys.COM Cc: sv-ac@eda-stds.org; sv-cc@eda.org Subject: RE: [sv-ac] call to vote on 1503 Hi Dmitry and Bassam, I vote yes if the following comments are considered: 1. There are two 36.41 Clocking Block diagrams and the second one does not reflect the changes from the first one. This might confuse the editor. Can they be combined or minimally move the first one to after the second one. [Bassam] These are 2 distinct fixes, the 1st is assertion related, the 2nd was a bug I found along the way in the diagramming (dashed line vs. not), I seriously doubt this is an issue to editor. 2. In 36.76 Let declaration, a. I think you need to cross out the vpiDefFile and vpiDefLineNo as was done on the other diagrams. [Bassam] Good catch, I think this has no detrimental effect, just an extra cleanup that can be done - please file a separate mantis and yank the diagram to post a proposal. b. Is "seq formal decl" correct? It can only be a boolean expression, not a sequence or a named event [Bassam] Yes, this covers the Boolean case. A note can be added for a semantic restriction please file mantis item with a detail note added. 3. "The cbAssertionStart, cbAssertionSuccess, and cbAssertionFailure callbacks may also be registered on a sequence instance or a property instance." This is almost true. The property or sequence instance MUST be contained in an assertion statement. For example, a sequence that is instantiated in a property that is never asserted will never Start, Succeed, or Fail. How about: "The cbAssertionStart, cbAssertionSuccess, and cbAssertionFailure callbacks may also be registered on a sequence instance or property instance that is instantiated in an assertion statement." [Bassam] Same can be said for any sequence that is never triggered like 0 ##1 seqhere. I think the form you suggest is confusing to me about instantiation context .In general one can register a CB it may never trigger for a variety of reasons. "may" should cover the loopholes I think. 4. 38.5.2 "verification statements" should be "assertion statements" (2 times) [Bassam] Yeah I remember we had another proposal for the chapter ones, not sure how best to tackle the editorial fix here. 5. I am confused as to why vpiClockedProp exists. There is no diagram for "clocked property" as there is for "clocked seq" Should there be? [Bassam] Yes, see 36.45 Lisa [Bassam] AIs: Bug (find a way to address): #4 - Dmitry I suggest we find a way to "fix" likely Editor will do without specifying but if we can add a note/update somehow would be great. Enhancements: (new mantis items) #2 a) cross out extras of vpiDefFile/LineNo. #2 b) add a detail to clarify the let formals. ________________________________ From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Korchemny, Dmitry Sent: Friday, April 11, 2008 11:43 AM To: sv-ac@eda.org Subject: [sv-ac] call to vote on 1503 Hi all, This is the call to vote on the proposal for 1503. SV-CC has already approved this proposal. The document on Mantis is 1503_latest.pdf Please, vote if you are eligible. Dmitry ------------------------------------------------------------------------ ---------- Ballot on Mantis 1503 - Called on 2008-04-11, final ballots due by 2008-04-14 T 23:59-08:00 PDT. v[xxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxxx-xx] Doron Bustan (Intel) v[xx-xxxxxxxxxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx-x] Eduard Cerny (Synopsys) n[-----------------------------------x-xxx---------x-x-xxx-x---x] Surrendra Dudani (Synopsys) v[xxxxxxxxxxx-xxxxxxxxx-xxxxxx-xxxxxxxxx-xx-xxxxx-xxx-xxx-------] Yaniv Fais (Freescale) v[xxxxxxxxxxxxxxxxx--xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx] John Havlicek (Freescale) t[xxxx-xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxrxxxxxxxxxxxxx-xxx] Dmitry Korchemny (Intel - Chair) y[xx--xx-x-xxxxxxxxx-xxxxxxxxx-xxx-x--xx--xxxxx----------xx-xxxx] Manisha Kulshrestha (Mentor Graphics) n[----------x-x-------------------------------------------------] Ah-Lam Lee (Qualcomm) n[--------------------------------------------xxxxx-------x-xx-x-] Jiang Long (Mentor Graphics) n[-x--------------------x------------x--xxx....................] Joseph Lu (Altera) n[--------x-x--xxxxxxxxxxxxxxxxxxx.............................] Johan Martensson (Jasper) n[----------------------------------------x--x-xx--xx-xxxxxxx-x-] Hillel Miller (Freescale) v[xx-xxxxxxxxxxxxxxx-xxxx-xxxxxxxxxxxxxxxxxxx-xxxxxxxx-xxxxxxxxx] Lisa Piper (Cadence) v[x-xxxxxx-xxxxxxxxxx-x-x-xx-xxxxxxx-x-xxxxx-x.................] Erik Seligman (Intel) n[--------------------x-x----x--------xxxx-----xxxx-xx----------] Tej Singh (Mentor Graphics) v[xx-x-x-x-xxx-xxxxxx-x-xxxxxx--xxxxxxxx-xxxxxxxxxxxxxxxxxxxxxxx] Bassam Tabbara (Synopsys) v[xxxxxxxxxxxxxxxxxxxxxx-xxxxxxxxxxxxx-xxxxxxxxxx...............] Tom Thatcher (Sun Microsystems - Co-Chair) |------------------------------------------------------ attendance on 2008-04-08 |-------------------------------------------------------- voting eligibility on 2008-04-08 Legend: x = attended - = missed r = represented . = not yet a member v = valid voter (2 out of last 3 or 3/4 overall) n = not a valid voter t = chair eligible to vote only to make or break a tie --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). 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