[sv-cc] Simpler proposal for JEITA concerns

I have uploaded a proposal for a much less radical and much less far-
reaching response to JEITA's request in Mantis item 1835.  The proposed 
changes take up only three pages.  The proposal primarily does three 
things:

-- In the places that define the scope of VPI, it expands the scope to 
include not only behavioral and structural constructs but also 
assertion and coverage constructs.

-- It retains a separate reference to the coverage API for the parts of 
the coverage API that are not included in VPI.

-- It uniformly changes the name for "Verilog Procedural Interface" 
(and in one case, "Verilog programming interface") to "SystemVerilog 
Verification Procedural Interface," to accommodate objections to 
keeping the now presumably deprecated "Verilog" as part of the name.

I believe this is likely to meet JEITA's real concerns without 
requiring a massive rethinking of the language of the document.

Regards,
Jim Vellenga

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Software Architect                     (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information." 
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