The quick, jocular answer is because some things have names but don't have full names. Historically, an object was supposed to have a full name if you could use that full name to find the object using vpi_handle_by_name(<full_name>, NULL). With the advent of SystemVerilog, we now have objects that don't have a fixed relationship to the design root, or perhaps a relationship that we've not yet decided to codify. Let's consider the in-flight vpiClassTypespec objects, for example. The proposal says that if the vpiClassTypespec represents a class specialization, it shall a valid though tool-dependent name. If that tool-dependent name is the same as the name of the corresponding vpiClassDefn, then we have an ambiguity if we try to embed that name in a full name. I think we probably could, but at least one of the vendors (namely, the one I work for) doesn't yet have enough experience to lock down on a particular choice. And even if we did, we'd have to convince the other vendors. That probably won't happen in the current round. For a vpiTypespecMember, the vpiName is the identifier for that member, but it does not (in this context) name a particular member of a particular struct, and so does not have a full name. Similarly, we have not yet figured out how to specify a full name for typespecs in general. We probably could, but then what would one use it for? Again, we don't within the normal VPI use model provide a vpiFullName for a task or function call. Part of the reason for this is that VPI allows you to go from a context (such as a containing statement or other expression) to an expression, but we're not set up to compute the reverse relation. And if multiple instances of a function call are embedded in the same containing other expression, what kind of full name could you construct? But it does make sense to return the identifier of the corresponding task or function declaration. So I expect it's just a buncha different reasons. Regards, Jim Vellenga --------------------------------------------------------- James H. Vellenga 978-262-6381 Software Architect (FAX) 978-262-6636 Cadence Design Systems, Inc. vellenga@cadence.com 270 Billerica Rd Chelmsford, MA 01824-4179 "We all work with partial information." ---------------------------------------------------------- ________________________________ From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Bresticker, Shalom Sent: Tuesday, August 26, 2008 9:45 AM To: SV-CC Subject: [sv-cc] vpiName Hi, In the VPI diagrams, why does vpiName sometimes appear without vpiFullName as well? Thanks, Shalom Shalom Bresticker Intel Jerusalem LAD DA +972 2 589-6582 +972 54 721-1033 --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner <http://www.mailscanner.info/> , and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Aug 26 08:00:06 2008
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