[sv-cc] Question regarding vpi_get_delays()

Hello!
 
Does anyone knows what delays VPI should return when getting delays of
vector module path annotated from SDF with different delay for every
bit?
I want to emphasize that delay is obtained with a handle to the WHOLE
vector (module path).
 
I do not include VPI application for code brevity since its purpose is
clear - getting delays of module path.
 
See the example:
 
// Verilog
module my(o, i);
 output [3:0] o;
 input [3:0] i;
 
 buf (o[3], i[3]);
 buf (o[2], i[2]);
 buf (o[1], i[1]);
 buf (o[0], i[0]);
 
 specify
 (i => o) = 30; // <--- getting delay for this path annotated with SDF
 endspecify
endmodule
 
module my_top;
 wire [3:0] o;
 reg [3:0] i;
 
 my uut(o, i);
 
 initial $sdf_annotate("my.sdf");
endmodule
 
// SDF
(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "and_INTERCON_001")
  (DATE "Tue Jul 20 12:08:53 1999 ")
  (VENDOR "Xilinx")
  (PROGRAM "Xilinx VERILOG SDF writer")
  (VERSION "M1.5.25")
  (DIVIDER /)
  (VOLTAGE 5.00:5.00:5.00)
  (PROCESS "best=1.0:nom=1.0:worst=1.0")
  (TEMPERATURE 25.00:25.00:25.00)
  (TIMESCALE 1 ns)
  (CELL
    (CELLTYPE "my")
      (INSTANCE uut)
        (DELAY
          (ABSOLUTE
            (IOPATH i[3] o[3] (90))
            (IOPATH i[2] o[2] (80))
            (IOPATH i[1] o[1] (70))
            (IOPATH i[0] o[0] (60))
          )
        )
  )
)
 
 
Best Regards,
 
Krzysztof Konopko
Software Engineer
Aldec

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