[sv-cc] DPI class/object reference passing feature

SV-CC team,

I wanted to let you know that there is a significant interest in the DPI standardization of object reference passing, i.e. information passed for classes. I am the co-chair of the Accellera Verification IP committee and work for Intel's RTL & Validation solutions team. This is a big deal for both parties. Our interest lies on mixed-language support of the Universal Verification Methodology (UVM), an Accellera effort to standardize a base class library and methodologies, bringing together the best of OVM and VMM. This DPI feature is the key element needed to support a standardization mechanism for mixed-language support in the UVM.

I'll work with my Intel colleagues, do we have anyone on the CC team?, to push our interests here. I wanted to express to you how important this feature is to Intel and to the industry. Please let me know if I can help in this effort in any way. I am on the sv-bc and sv-ec teams and can step in to help define and propose this feature if needed.

Thanks, -Tom

-----Original Message-----
From: vip-tc@lists.accellera.org [mailto:vip-tc@lists.accellera.org] On Behalf Of Slater Rob-R53680
Sent: Thursday, May 27, 2010 12:52 PM
To: vip-tc@lists.accellera.org
Subject: [Accellera:vip-tc] TLM2 Or Not 2 TLM2

Hi,

I thought more about the TLM2 "discussion" yesterday on the call.

I think the motivation driving TLM2 is to:
(1) have proper, standard object interconnect within UVM
(2) Also, when the time is right, we'd like to have the flexibility to
extend
    or replace UVM reference models with SystemC ones. To make this as
easy
    as possible, the reference models developed in pure-UVM need to
already
    have the TLM2 connections and timing mechanisms

Regarding (2): The biggest limitation to implementing this is the lack
of standard way to pass C++ objects through the VPI/DPI. I don't think
getting something hacked together would be too difficult for the EDA
companies (for well-defined C++ structures).

But clearly is this the domain of the SV-CC to define and I hope that it
is defined real soon now.

Regarding (1): Having proper interconnect is desirable even if only in
UVM. The OVM way of doing things is a bit of a hack as Mohammad noted
in his presentation yesterday.

Also, if the VPI/DPI gets to where it needs to be it will be a shame if
legacy UVM reference models won't be able to connect to the SystemC
world.

Referring to the numbering in Mohamed & Janick's proposal presented
yesterday, I suggest that the VIP-TC do the following:

(1) Enhanced Communication Tools:
I strongly suggest that the VIP TC investigate and prototype a sub-set
of TLM2 is worth implementing in the UVM 1.0 time frame in order to
accomplish goal (1).

(2) Foreign Language Interface:
Punt until the DPI/VPI standard is where it needs to be.

(3) Block to Top Test Reuse
Seems to come with (1)

(4) Timed Modeling
Same strategy as (1)

Rob Slater
Freescale Semiconductor

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