Date: Thu Jul 26 2012 - 09:47:25 PDT
I consider this an obvious typo and would be willing to correct it in the
next draft without a Mantis item.
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
Sutherland HDL, Inc.
22805 SW 92nd Place
Tualatin, OR 97062
stuart@sutherland-hdl.com
+1-503-692-0898
Training engineers to be Verilog, SystemVerilog and UVM wizards!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Thursday, July 26, 2012 6:53 AM
To: Radoslaw Nawrot; sv-cc@eda.org
Subject: RE: [sv-cc] Bug in process object model diagram
Yes, there were a few similar cases in the past (Manti 58, 785, 2063, 2427,
2623).
Shalom
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Radoslaw
Nawrot
Sent: Thursday, July 26, 2012 16:38
To: sv-cc@eda.org
Subject: [sv-cc] Bug in process object model diagram
Hello,
I think there is a bug in 37.58 Process
there is
bool:vpiAlwaysType
should be
int:vpiAlwaysType
I did not found mantis on that
Regards,
Radek
---------------------------------------------------------------------
Intel Israel (74) Limited
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
