RE: [sv-cc] Array of net on module port

So it propose to change (37.14 Ports): 
 

6) Properties vpiScalar and vpiVector shall indicate if the port is 1 bit or
more than 1 bit. They shall not indicate
anything about what is connected to the port.

 

to:

 

6) A port without a packed dimension defined is a scalar; and for that
object, the property vpiScalar shall return TRUE and the property vpiVector
shall return FALSE. 

    A port with one or more packed dimensions defined is a vector, and the
property vpiVector shall return TRUE (vpiScalar shall return FALSE). 

 

 

Radek

 


  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Tuesday, June 04, 2013 4:08 PM
To: Radoslaw Nawrot; sv-cc@eda.org
Subject: RE: [sv-cc] Array of net on module port



Ø  Maybe we should treat ports ther same way as nets?

 

I would think so.

Probably when this detail was added for nets, no one thought about ports.

 

Shalom

 

From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Radoslaw
Nawrot
Sent: Tuesday, June 04, 2013 10:57
To: sv-cc@eda.org
Subject: [sv-cc] Array of net on module port

 

Hello,

I have an example:

 

module top;
wire X [5];
test TEST(X);

.....

endmodue

 

module test(output OUT[5]);

...

 

endmodule

 

 

LRM says:

for net's (37.16 Nets):

25) A logic net without a packed dimension defined is a scalar; and for that
object, the property vpiScalar shall return

TRUE and the property vpiVector shall return FALSE. A logic net with one or
more packed dimensions defined is

a vector, and the property vpiVector shall return TRUE (vpiScalar shall
return FALSE). Packed struct nets and

packed array nets are vectors, and the property vpiVector shall return TRUE
(vpiScalar shall return FALSE). A net

bit is a scalar, and the property vpiScalar shall return TRUE (vpiVector
shall return FALSE). (..) For an array net, the

vpiScalar and vpiVector properties shall return the values of the respective
properties for an array element. The

vpiScalar and vpiVector properties shall return FALSE for all other net
objects.

 

for ports (37.14 Ports):

6) Properties vpiScalar and vpiVector shall indicate if the port is 1 bit or
more than 1 bit. They shall not indicate
anything about what is connected to the port.

 

 

So 

X :

scalar : true

vector : false

 

OUT: 

scalar: false

vector: true

 

 

Is it correct?

Maybe we should treat ports ther same way as nets?

 

Regards,

Radek

 


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