[sv-cc] vpiInterModPath with delays in Verilog code

Hello,
I have question about vpiInterModPath.
Does it work with Verilog/SystemVerilog constructs (
i.e
assign #10 x=y;
 
or wire #10 w;
)
or only with delays from sdf files?
 
Thanks in advance,
Radek
 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.