RE: [sv-cc] vpiInterModPath with delays in Verilog code

I was trying to get InterModPath between two ports connected to wires with
short with delay
Now it's clear to me that I must check it using vpiDelay,
Thanks.

Radek
  _____  

From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com] 
Sent: Wednesday, July 03, 2013 12:17 PM
To: Radoslaw Nawrot; sv-cc@eda.org
Subject: RE: [sv-cc] vpiInterModPath with delays in Verilog code



As I understand it, vpiInterModPath refers to intermodule path delays.

 

Just as the name says, they are between modules.

 

The constructs you asked about are within a module.

 

In fact, 37.3.4 says,

 

Nets, primitives, module paths, timing checks, and continuous assignments
can have delays specified within

the SystemVerilog source code. Additional delays may exist, such as module
input port delays or intermodule

path delays, that do not appear within the SystemVerilog source code. To
access the delay

expressions that are specified within the SystemVerilog source code, use the
method vpiDelay.

 

Regards,

Shalom

 

From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Radoslaw
Nawrot
Sent: Wednesday, July 03, 2013 12:51
To: sv-cc@eda.org
Subject: [sv-cc] vpiInterModPath with delays in Verilog code

 

Hello,
I have question about vpiInterModPath.
Does it work with Verilog/SystemVerilog constructs (
i.e
assign #10 x=y;

 

or wire #10 w;
)
or only with delays from sdf files?

 

Thanks in advance,

Radek

 


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