RE: V-AMS DevModeling meeting April 6, new proposal doc

I guess I am somewhat confused. When you have SystemVerilog-AMS (which is what I have been told by Vassilios you are working on and
what the board has approved as the next version) then you have all of the keywords in SV. I do not understand the comment of merging
in pieces. SV is an approved and completed standard. Why in pieces?

Regards
David

-----Original Message-----
From: owner-verilog-ams@eda.org [mailto:owner-verilog-ams@eda.org] On Behalf Of Geoffrey.Coram
Sent: Monday, April 05, 2004 11:36 AM
To: David W. Smith
Cc: 'Kevin Cameron'; 'Verilog-A Reflector'; verilog-ams-devmod@eda.org
Subject: Re: V-AMS DevModeling meeting April 6, new proposal doc

David -
We don't need "ref" as a keyword, so I don't see any reason to
inflict that pain now. The merge with SystemVerilog will likely
cause a lot of pain, and it could destroy Verilog-A if that
merge were done in pieces, so every N months, everyone has to go
through the whole library of Verilog-A modules and figure out
what needs to be changed.

I also wouldn't be surprised if a number of Spice simulators
only ever implemented Verilog-A 2.2 (or whatever these
extensions become) -- not even the full AMS.

-Geoffrey

"David W. Smith" wrote:
>
> Just a quick comment. You are going to have to eventually accept all of the new keywords in SystemVerilog anyway so the argument
that ref may collide (while true) is not particularly relevant. Changing the syntax will not be an option since SystemVerilog is now
an approved standard.
>
> Regards
>
> David
Received on Mon Apr 5 11:38:51 2004