RE: Verilog-AMS question regarding retention

Marq,

This is an interesting detail I missed.  According to this:
"with the initial condition computed or assigned in DC analysis"
if the idt statement is not part of the initial condition
calculations, it should return results as if IC was omitted,
i.e. IC=0?  So the two examples below are supposed to CORRECTLY
return the same results?

  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap), V0) / Cap_value;
  -------------------------------------------
  if (analysis("static"))
    some stuff here;
  else
    V(cap) <+ idt(I(cap)) / Cap_value;

Is this the intention of the LRM, and considered the correct
behavior?

Arpad
=================================================================

This is an excellent point: the LRM says that the idt() operator 
should run from 0 to t, with the initial condition computed or 
assigned in DC analysis. Now what happens if the simulation 
starts at some other time, for instance to have some control logic 
in a particular state? It should start from t0, where t0 is the 
time value of the (implicit) DC analysis