Arpad, As I have read the LRM the subtle difference between ic being omitted and ic=0 is that in the first case the implicit DC provides the initial condition, while in the second one explicitly sets the initial condition to 0. One example that I can think of is two identical capacitors in series: if a voltage is applied to the pair, you'd expect the voltage in between to be half of the total voltage: it's a capacitive voltage divider. Now if one is given an ic=0, the voltage in between would be either 0 or the full voltage, depending on which of the capacitors is connected to ground. Now what happens if both ic values are set to 0? I've run this experiment with our in-house simulator which gives exactly the above results. With both capacitors having an ic=0, apparently the ic data are discarded. Marq owner-verilog-ams@eda.org wrote on 12-10-2005 18:26:02: > Marq, > > This is an interesting detail I missed. According to this: > "with the initial condition computed or assigned in DC analysis" > if the idt statement is not part of the initial condition > calculations, it should return results as if IC was omitted, > i.e. IC=0? So the two examples below are supposed to CORRECTLY > return the same results? > > if (analysis("static")) > some stuff here; > else > V(cap) <+ idt(I(cap), V0) / Cap_value; > ------------------------------------------- > if (analysis("static")) > some stuff here; > else > V(cap) <+ idt(I(cap)) / Cap_value; > > Is this the intention of the LRM, and considered the correct > behavior? > > Arpad > ================================================================= > > This is an excellent point: the LRM says that the idt() operator > should run from 0 to t, with the initial condition computed or > assigned in DC analysis. Now what happens if the simulation > starts at some other time, for instance to have some control logic > in a particular state? It should start from t0, where t0 is the > time value of the (implicit) DC analysis >Received on Thu Oct 13 02:19:51 2005
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