RE: Verilog-AMS question regarding retention

From: Jonathan David <j.david_at_.....>
Date: Thu Oct 13 2005 - 11:34:32 PDT
Actually it wouldn't.. since only 1 of the statements
will contribute, and the other wouldn't.. 
so the one evaluated last will either contribute
something or zero..

My practice here has been to stick to the spirit and
avoid switch branches where possible.. 
Jonathan

derivVb = ddt(V(b));
I(b) <+ (V(b_sw)>vth)? V(b)/Rmin: parasitic_cap *
derivVb


--- Marq Kole <marq.kole@Philips.com> wrote:

<<snip>> 
> By the way, analog operators are not allowed in
> conditional or case 
> statements, but the LRM says nothing about the use
> of relational or 
> equality operators, like in:
> 
>   branch b_sw(ctrl, gnd);
>   branch b_1(plus, minus);
>   branch b_2(plus, minus);
> 
>   analog
>     V(b_1) <+ (V(b_sw) == 1) * I(b_1) * Rmin;
>     I(b_2) <+ (V(b_sw) == 0) * parasitic_cap *
> ddt(V(b_2));
>   end
> 
> This would be a switch with resistance in the
> on-state and parasitic 
> capacitance in the off-state.
> 
=== message truncated ===
Received on Thu Oct 13 11:34:37 2005

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