Re: multiple analog blocks

Kevin Cameron wrote:
> 
> The meaning of "The domain of a variable is that of the context
> from which its value is assigned." in 8.2.2 is not clear, and
> variables don't actually need to be assigned a domain, only
> drivers and receivers need to be considered as belonging a
> domain, but there is no real reason you can't assign to
> "analog" objects in a digital process or "digital" objects
> from an analog.

I haven't really though through all the ramifications, and
I don't really know what "drivers" and "receivers" are for
a compact model ... but the LRM also says "the derivative
with respect to time of a digital value is always zero (0)."

So, now if I have 
  I(a,c) <+ ddt(qdep);
where qdep is usually computed in the analog section, but
at some points in the digital simulation one sets qdep=0,
then what happens to the current?

> > A major benefit of Verilog-A (over VHDL-AMS) is, in fact, that it *is*
> > a proper language, with a well-defined subset defined in the LRM.
> >
> Not really, the fact that OVI agreed to let Verilog-A exist
> as an intermediate step has led to people treating it as a
> standalone language, but it was never meant to exist for long.
> The original goal was to have a single AMS language. Ken
> campaigned for the subset approach and after the Verilog-A LRM
> was released he and the other Cadence representatives on this
> committee went to great lengths to stall the process of
> releasing a Verilog-AMS LRM. That's why SystemVerilog is now
> a separate standard off at the IEEE without any analog capability.

I would say that the fact that Verilog-A is a well-defined
standard is the reason why it has been formally adopted as 
the language of choice for most of the compact model
development teams and why the GEIA Compact Model Council
accepts models in Verilog-A for standardization.

That SV has no analog capability is a separate issue, which
continues to this day, evidenced by the fact that there is 
still little commitment from the SV committees to merging in
AMS.

Of course, the origins of Verilog-A were well before my time
on this committee, so I don't know what OVI's intention was --
nor Ken's, and I don't think it's appropriate to speculate.

-Geoffrey