Re: multiple analog blocks

All,
    Apparently my message has rekindled an old feud. I apologize to all
of you for that. For many years I have limited my involvement in the
Verilog-A/MS committee in order to spare everyone from this
unpleasantness. The committee has been operating smoothly and
effectively all that time and I was hoping that the old wounds would
have healed and that I could return to being an active and contributing
member. Allow me to work with Kevin to see if we can get past this. And
please rest assured that I have never tried to stall Verilog-AMS. I did
many things wrong in those early days, but that is not one of them. In
fact, much of the early tension in the committee results from my being
overly aggressive about getting Verilog-A released, but that was before
Kevin was involved and so he might not be aware of it.

Kevin,
    Let me start for apologizing for my behavior in the past. Now that I
am older I can look back and see that when I was working in both the
Verilog-A and VHDL-A committees I was pretty immature, and as a result I
was arrogant and confrontational. I regret the effect that my behavior
has had on you and others (are you out there Dan, Ernst, ...) and on the
languages. Please forgive me.

-Ken

Kevin Cameron wrote:
> Ken campaigned for the subset
> approach and after the Verilog-A LRM was released he and the other
> Cadence representatives on this committee went to great lengths to stall
> the process of releasing a Verilog-AMS LRM.