Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

edaorg@v-ms.com wrote:
> 
> > analog begin
> > I(a,b) <+ 0;
> > if(P)
> >    V(a,b) <+ 5;
> > end
> 
> Why would you do that?

I(a,b) <+ 0 is the "default" state of a branch.
One could then have the V() contrib based on some
condition.

For example, I had a designer here suggest an
approach for modeling power-up of a part with a
current source that feeds 0A at first, then feeds
500mA until the voltage reaches the target 5V,
and then acts like a voltage source for the
remainder of the simulation.

-Geoffrey

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