Re: Verilog-AMS Committee Meeting Minutes - Dec 22 2006

Geoffrey.Coram wrote:
> edaorg@v-ms.com wrote:
>   
>>> analog begin
>>> I(a,b) <+ 0;
>>> if(P)
>>>    V(a,b) <+ 5;
>>> end
>>>       
>> Why would you do that?
>>     
The comment referred to the whole paragraph, i.e. that snippet was the 
concatentation of the bits above (you didn't quote), so the question was 
really: "why would you do the concatentation?"

Sorry about the lack of clarity.

Kev.

> I(a,b) <+ 0 is the "default" state of a branch.
> One could then have the V() contrib based on some
> condition.
>
> For example, I had a designer here suggest an
> approach for modeling power-up of a part with a
> current source that feeds 0A at first, then feeds
> 500mA until the voltage reaches the target 5V,
> and then acts like a voltage source for the
> remainder of the simulation.
>
> -Geoffrey
>
>   

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