Re: real-to-integer conversion

All,

And the same text is also present in subsection 4.1.1.1 - do we really need
to hammer this home? :-)

Cheers,
Marq

owner-verilog-ams@server.eda.org wrote on 16-10-2007 15:14:14:
> All,
>
> The current Verilog-AMS update proposals for chapter 2 and chapter 3
> contain duplictae information: the first paragraph of section 3.1.1
> is essentially the same as section 2.5.4. Considering that
> conversion is not a lexical convention I would suggest to remove it
> from section 2.5.4 and provide the additional examples of conversion
> in this subsection to section 3.1.1.
>
> Cheers,
> Marq
>
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