XC9500
In-System Programmable (ISP)
CPLD-Family
The
XC9500™ In-System Programmable (ISP) CPLD family takes complex programmable
logic devices to new heights of high-performance, feature-richness, and
flexibility. This family delivers industry-leading speeds, while giving
you the flexibility of an enhanced customer proven pin-locking architecture
along with extensive IEEE Std. 1149.1 JTAG boundary scan support. It features
six devices ranging from 36 to 288 macrocells with a wide variety of package
combinations that both minimize board space and maintain package footprints
as designs grow or shrink. All I/O pins allow direct interfacing to both
3 and 5 volt systems, while the latest in compact, easy-to-use CSP and
BGA packaging gives you access to as many as 192 signals.
Family Highlights
Highest density
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5 ns pin-to-pin logic delays on all pins
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fCNT to 125 MHz
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Competitively Priced
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Wide range of package styles including new Chip Scale
Packaging (CSP)
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Wide Density Range
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36 to 288 macrocells (800 to 6,400 gates)
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34 to 192 I/Os
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Customer Proven Pin-Locking Architecture
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Flexible 36V18 function block
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90 product terms drive any or all of 18 macrocells
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Global and product term clocks, output enables, set
and reset
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Power selection for each macrocell
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Designed for True 5 Volt In-System Programmability
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Industry standard JTAG interface
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Endurance of 10,000 program/erase cycles
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Device programming over the full voltage and temperature
range
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20 years data retention
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Programmable Outputs
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24 mA drive on all pins
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3.3 V or 5 volt I/O capability
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Slew rate control on each output
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Industry-Leading JTAG Boundary Scan Support
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Extended boundary scan functions
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On-chip logic testing
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High impedance I/O isolation
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ID and USER Codes
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Design security
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Write Only (no readback) function
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Seamless Integration of ATE and Third-Party JTAG Programming and Test
Tools
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Automatic test system programming support
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Extensive third-party tool support
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JTAG Technologies
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Corelis Incorporated
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ASSET Intertech
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Easy-to-Use Design Tools: Alliance and Foundation Series Software Support
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Windows NT, Windows 95, SunOS, Solaris, HPUX
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Standards-based design flows
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Open third-party EDA systems integration with the
Alliance Series Software
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Complete, stand-alone solutions with the Foundation
Series Software
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Flexible Pin-Locking Architecture
The XC9500 devices, in conjunction with our fitter software, gives
you the maximum in routability and flexibility while maintaining high performance.
The architecture is feature rich, including individual p-term output enables,
three global clocks, and more p-terms per output than any other CPLD. The
proven ability of the architecture to adapt to design changes while maintaining
pin assignments (pin-locking) has been demonstrated in countless real-world
customer designs since the introduction of the XC9500 family. This assured
pin-locking means you can take full advantage of in-system-programmability
and you can easily change at any time, even in the field.
Full IEEE 1149.1 JTAG Development and Debugging Support
The JTAG capability of the XC9500 family is the most comprehensive
of any CPLD on the market. It features the standard support including BYPASS,
SAMPLE/PRELOAD, and EXTEST. Additional boundary scan instructions, not
found in any other CPLD, such as INTEST (for device functional test), HIGHZ
(for bypass), and USERCODE (for program tracking), allow you the maximum
debugging capability.
The XC9500 family is supported by a wide variety of industry standard
third-party development and debugging tools including Corelis, JTAG Technologies,
and Asset Intertech. These tools allow you to develop boundary scan test
vectors to interactively analyze, test, and debug system failures. The
family is also supported on all major ATE platforms including Teradyne,
Hewlett Packard, and Genrad.
Leadership FastFLASH™ Technology
Xilinx is the innovator in Flash technology designed specifically for
high-performance CPLDs. The superior pin-locking capability of the XC9500
family is made possible by a dense internal switch matrix with over three
times the routing switches of any other ISP CPLD. FastFLASH cells that
are 1/3 the size of EEPROM cells bring you the benefits of high-density
and high-performance along with the added benefit of 10,000 program/erase
cycles to assure complete product life cycle support. The rapid growth
and rapid development of memory-based flash technologies assures you of
lower product costs along with multiple, competitive, state-of-the-art
fabrication sources.
Powerful Software Tools
Advanced fitter algorithms and powerful "auto-interactive" features
allow you to choose between pushbutton and manual design flows, and standards-based
design-flows including EDIF, SDF, VHDL (VITAL), and Verilog. Both the Alliance
Series and Foundation Series software include the JTAG software and the
JTAG cable required for ISP JTAG programming of all XC9500 products.
| XC9500 Product Overview |
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XC9536 |
XC9572 |
XC95108 |
XC95144 |
XC95216 |
XC95288 |
| Macrocells |
36 |
72 |
108 |
144 |
216 |
288 |
| Usable Gates |
800 |
1,600 |
2,400 |
3,200 |
4,800 |
6,400 |
| tPD (ns) |
5.0 |
7.5 |
7.5 |
7.5 |
10.0 |
15.0 |
| Registers |
36 |
72 |
108 |
144 |
216 |
288 |
| Maximum User I/Os |
34 |
72 |
108 |
133 |
166 |
192 |
| Packages |
48CSP |
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44VQ |
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44PC |
44PC |
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84PC |
84PC |
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100TQ |
100TQ |
100TQ |
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100PQ |
100PQ |
100PQ |
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160PQ |
160PQ |
160PQ |
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208HQ |
208HQ |
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352BG |
352BG |
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