The ProASIC3E Clock Conditioning Circuit (CCC) contains a PLL core, delay lines, clock multipliers/dividers, PLL reset generator (you have no control over the reset), global pads, and all the circuitry for the selection and interconnection of the “global” pads to the global network. The PLL Core consists of a Phase Detector, L.P. Filter, and a 4-Phase VCO.
The clock conditioning circuit performs the following basic functions:
Clock phase adjustment
Clock delay minimization
Clock frequency synthesis
In addition it also
Allows access from the global pads to the global network and the PLL block
Permits the three global lines on each side of the chip to be driven either by the global pads, core, and/or the outputs from the PLL block
Allows access from PLL to the core
The block contains several programmable dividers, each of them providing division factors 1, 2, 3, 4……k (where k depends on the number of bits used for the division selection). Overall, you can define a wide range of multiplication and division factors, constrained only by the PLL frequency limits, according to:
m/(n*u)
m/(n*v)
m/(n*w)
The clock conditioning circuit block performs a positive / negative clock delay operation in increments of 160ps, of up to 5.56ns (at 1.5V, 25C, typical process) before or after the positive clock edge of the incoming reference clock. Furthermore, the system allows for the selection of one of four clock phases of fout, at 0, 90, 180 and 270 degrees.
A “Lock” signal is provided to indicate that the PLL has locked on to the incoming signal. A “Power-down” signal switches off the PLL block when it is not used.
The input clock, fin, is first passed through the adjustable divider (FINDIV) prior to application to the PLL core, phase detector's PLLFIN input.
The feedback signal, to which fin is compared, can be selected from several sources, giving the CCC its flexibility. All sources of the feedback signal can be divided by 1, 2, 3, …128 in divider FBDIV. This has the effect of multiplying the input signal. The source signals are:
The VCO output signal, with 0 degree phase shift and zero additional time delay
A delayed version of the VCO output, in selectable increments of 160ps, up to 5.56ns
An external feedback signal from I/O
Each of the above feedback source signals can be further delayed by a fixed amount designed to emulate the delay through the chip’s clock tree. This allows for clock-line de-skewing operations.
When the loop has acquired lock, the Lock Detect signal will be asserted. This signal will be available to the logic core, via the output port LOCK.
Once locked, the various output combinations will be available to the Global lines.
The PLL can be placed in power-down mode by setting the power down signal PWRDWN to low. When in power-down mode, the PLL draws less than 100mA of current and sends 0V signals on all outputs.
See Also
Configure Clock Conditioning / PLL cores