import_source [-merge_timing value][-merge_physical value][-merge_all value][-format file_type [-abort_on_error][-top_entity][-flavor value]filename
-merge_timing value
Specifies whether to preserve all existing timing constraints when you import an SDC file. Same as selecting or unselecting the "Keep existing timing constraints" check box in the Import Files dialog box. The following table shows the acceptable values for this option:
|
Value |
Description |
|
yes |
Designer merges the timing constraints from the imported SDC file with the existing constraints saved in the constraint database. If there is a conflict, the new constraint has priority over the existing constraint. |
|
no |
All existing timing constraints are replaced by the constraints in the newly imported SDC file. |
-merge_physical value
Specifies whether to preserve all existing physical constraints when you import a GCF or PDC file. Same as selecting or unselecting the "Keep existing physical constraints" check box in the Import Files dialog box. The following table shows the acceptable values for this option:
|
Value |
Description |
|
yes |
Designer preserves all existing physical constraints that you have entered either using one of the MVN tools (ChipPlanner, PinEditor, or the I/O Attribute Editor) or a previous GCF or PDC file. The software resolves any conflicts between new and existing physical constraints and displays the appropriate message. |
|
no |
All existing physical constraints are replaced by the constraints in the newly imported GCF or PDC file. |
-merge_all value
Specifies whether to preserve all existing physical and timing constraints when you import an SDC and/or a PDC file. Same as selecting or unselecting the "Keep existing physical constraints" and "Keep existing timing constraints" check boxes in the Import Files dialog box. The following table shows the acceptable values for this option:
|
Value |
Description |
|
yes |
Designer preserves all existing physical constraints that you have entered either using one of the MVN tools (ChipPlanner, PinEditor, or the I/O Attribute Editor) or a previous GCF or PDC file. The software resolves any conflicts between new and existing physical constraints and displays an appropriate message. Any existing timing constraints from your ADB are merged with the new information from your imported files. New constraints override any existing timing constraints whenever there is a conflict |
|
no |
All the physical constraints in the newly imported GCF or PDC files are used. All pre-existing physical constraints are lost. Existing timing constraints from the ADB are replaced by the new timing constraints from your imported file. |
-format file_type
Specifies the file format of the file to import. You can import one of the following types of files: adl, edif, verilog, vhdl, gcf, pdc, sdc, or crt.
Note: Refer to Importing source files to know the formats supported for each family.
-abort_on_error
Aborts a PDC file if it encounters an error during import.
-top_entity
Specifies the top entity to a VHDL file.
-flavor
Specifies the type of netlist. It can be edif, viewlogic, or mgc.
filename
Specifies the name of the source file to import.
The -merge_timing, -merge_physical, and -merge_all arguments are available for ProASIC3/E, ProASICPLUS, Axcelerator and ProASIC families.
For source SDC (no PDC/GCF) in eX and SX-A:
import_source -merge_timing yes/no ...
import_source -merge yes/no ...
import_source -merge_all yes/no ...
For constraints in ProASICPLUS:
import_source -merge_physical yes/no ...
import_source -merge_all yes/no ...
import_source -merge yes/no ...
ProASIC does not support PreCompile import of the SDC files. The -merge_timing option has no effect on this import_source for ProASIC. The -merge_all and -merge options map to -merge_physical for ProASIC in import_source.
For ProASICPLUS, Axcelerator and ProASIC3/E:
import_source -merge_physical yes/no -merge_timing yes/no ...
import_source -merge_all yes/no ...
import_source -merge yes/no ...
The -merge_all and -merge options map to both -merge_physical and -merge_timing options for these families.
import_source \
-merge_physical "no" \
-merge_timing "yes"
-format "EDIF" -edif_flavor "GENERIC" \
{.\designs\mydesign.edn} \
-format "sdc" \
{.\designs\mydesign.sdc} \
-format "pdc" -abort_on_error "no" \
{.\designs\mydesign.pdc}
import_source \
-merge_physical "no" \
-format "verilog" \
{mydesign.v}
import_source \
-merge_physical "no" \
-merge_timing "no" \
-format "vhdl" -top_entity "aclass" \
{C:/mynetlist.vhd}
import_source \
-merge_physical "no" \
-merge_timing "no" \
-format "adl" {mydesign.adl}