// Tristate enable cell for inte_oen
    ENABLE inte_oen_cell(
        .EN     (inte_oen),
        .SHIFT  (bscan_shift),
        .SI     (o_132_so),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD     (bscan_sel_ff_out),
        .ENC_   (inte_oen_enc_l),
        .SO     (inte_oen_so)
    ) ;
 
    // Bidirectional pad for b_133 (inte_), enabled by inte_oen
// change to open drain for 2.0
// change to non pci so bond out doesn't change
    MEM_BI b_133_pad(
        .ENC_   (inte_oen_enc_l),
        .OT     (b_133_o),
        .TN     (w_input_tn),
        .SHIFT  (bscan_shift),
        .SI     (1'b0),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD1    (bscan_sel_ff_out),
        .MD2    (bscan_sel_ff_in),
        .PI     (i_129_po),
        .PO     (b_133_po),
        .SO     ( ),
        .IT     (b_133_i),
        .X      (b_133)
    ) ;
 

/* delete this and change to pci bi od for 2.0
    // Output pad for o_134 (cp_stat_l[1])
    MEM_OUT o_134_pad(
	.OT	(o_134_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_133_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_134_so),
	.X	(o_134)
    ) ;

*/
    // Tristate enable cell for intd_oen
    ENABLE intf_oen_cell(
        .EN     (intf_oen),
        .SHIFT  (bscan_shift),
        .SI     (inte_oen_so),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD     (bscan_sel_ff_out),
        .ENC_   (intf_oen_enc_l),
        .SO     (intf_oen_so)
    ) ;
 
    // Bidirectional pad for b_134 (intf_), enabled by intf_oen
// change to open drain for 2.0
// change to non pci so bondout doesn't change 
    MEM_BI b_134_pad(
        .ENC_   (intf_oen_enc_l),
        .OT     (b_134_o),
        .TN     (w_input_tn),
        .SHIFT  (bscan_shift),
        .SI     (1'b0),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD1    (bscan_sel_ff_out),
        .MD2    (bscan_sel_ff_in),
        .PI     (b_133_po),
        .PO     (b_134_po),
        .SO     ( ),
        .IT     (b_134_i),
        .X      (b_134)
    ) ;
 


    // Non-scanned output pad for o_ns_135 (ref_clk)
    MEM_OUT_NS o_ns_135_pad(
	.OT	(o_ns_135_o),
	.TN	(w_input_tn),
	.X	(o_ns_135)
    ) ;

/* delete this and change to pci bi open drain for 2.0
    // Input pad for i_136 (standby)
    MEM_IN i_136_pad(
	.X	(i_136),
	.SHIFT	(bscan_shift),
	.SI	(o_134_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_in),
	.PI	(i_129_po),
	.PO	(i_136_po),
	.SO	(i_136_so),
	.IT	(i_136_i)
    ) ;
*/

    // Tristate enable cell for intg_oen
    ENABLE intg_oen_cell(
        .EN     (intg_oen),
        .SHIFT  (bscan_shift),
        .SI     (intf_oen_so),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD     (bscan_sel_ff_out),
        .ENC_   (intg_oen_enc_l),
        .SO     (intg_oen_so)
    ) ;
 
    // Bidirectional pad for b_136 (intg_), enabled by intg_oen
// change to open drain for 2.0
// change to non-pci so bondout doesn't change -
    MEM_BI b_136_pad(
        .ENC_   (intg_oen_enc_l),
        .OT     (b_136_o),
        .TN     (w_input_tn),
        .SHIFT  (bscan_shift),
        .SI     (1'b0),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD1    (bscan_sel_ff_out),
        .MD2    (bscan_sel_ff_in),
        .PI     (b_134_po),
        .PO     (b_136_po),
        .SO     ( ),
        .IT     (b_136_i),
        .X      (b_136)
    ) ;
 
// uses the spare pin at v16

    // Tristate enable cell for inth_oen
    ENABLE inth_oen_cell(
        .EN     (inth_oen),
        .SHIFT  (bscan_shift),
        .SI     (intg_oen_so),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD     (bscan_sel_ff_out),
        .ENC_   (inth_oen_enc_l),
        .SO     (inth_oen_so)
    ) ;
 
    // Bidirectional pad for b_136 (intg_), enabled by intg_oen
// change to open drain for 2.0
// change to non-pci so bondout doesn't change
    MEM_BI b_136a_pad(
        .ENC_   (inth_oen_enc_l),
        .OT     (b_136a_o),
        .TN     (w_input_tn),
        .SHIFT  (bscan_shift),
        .SI     (1'b0),
        .CK     (bscan_clk_cap),
        .UP     (bscan_clk_upd),
        .MD1    (bscan_sel_ff_out),
        .MD2    (bscan_sel_ff_in),
        .PI     (b_136_po),
        .PO     (b_136a_po),
        .SO     ( ),
        .IT     (b_136a_i),
        .X      (b_136a)
    ) ;


    // Input pad for i_137 (input_reset_l)
//    MEM_IN_PU i_137_pad(
//  change to pull down per request on 2.0 
//  change scan in / parametric in for 2.0
    MEM_IN_PD i_137_pad(
	.X	(i_137),
	.SHIFT	(bscan_shift),
//	.SI	(i_136_so),
	.SI	(inth_oen_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_in),
//	.PI	(i_136_po),
	.PI	(b_136a_po),
	.PO	(i_137_po),
	.SO	(i_137_so),
	.IT	(i_137_i)
    ) ;

    // Dummy pad vss_138 ()
    // vss

    // Dummy pad vdd_139 ()
    // vdd

    // Input pad for i_140 (div_ctl[1])
    MEM_IN_PD i_140_pad(
	.X	(i_140),
	.SHIFT	(bscan_shift),
	.SI	(i_137_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_in),
	.PI	(i_137_po),
	.PO	(i_140_po),
	.SO	(i_140_so),
	.IT	(i_140_i)
    ) ;

    // Input pad for i_141 (div_ctl[0])
    MEM_IN_PD i_141_pad(
	.X	(i_141),
	.SHIFT	(bscan_shift),
	.SI	(i_140_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_in),
	.PI	(i_140_po),
	.PO	(po_out),
	.SO	(i_141_so),
	.IT	(i_141_i)
    ) ;

    // Output pad for o_142 (rom_addr[0])
    MEM_OUT o_142_pad(
	.OT	(o_142_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(i_141_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_142_so),
	.X	(o_142)
    ) ;

    // Output pad for o_143 (rom_addr[1])
    MEM_OUT o_143_pad(
	.OT	(o_143_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_142_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_143_so),
	.X	(o_143)
    ) ;

    // Dummy pad vss_144 ()
    // vss

    // Dummy pad vdd_145 ()
    // vdd

    // Output pad for o_146 (rom_addr[2])
    MEM_OUT o_146_pad(
	.OT	(o_146_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_143_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_146_so),
	.X	(o_146)
    ) ;

    // Output pad for o_147 (rom_addr[3])
    MEM_OUT o_147_pad(
	.OT	(o_147_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_146_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_147_so),
	.X	(o_147)
    ) ;

    // Output pad for o_148 (rom_addr[4])
    MEM_OUT o_148_pad(
	.OT	(o_148_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_147_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_148_so),
	.X	(o_148)
    ) ;

    // Output pad for o_149 (rom_addr[5])
    MEM_OUT o_149_pad(
	.OT	(o_149_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_148_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_149_so),
	.X	(o_149)
    ) ;

    // Dummy pad vdd_150 ()
    // vdd 

    // Output pad for o_151 (rom_addr[6])
    MEM_OUT o_151_pad(
	.OT	(o_151_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_149_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_151_so),
	.X	(o_151)
    ) ;

    // Output pad for o_152 (rom_addr[7])
    MEM_OUT o_152_pad(
	.OT	(o_152_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_151_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_152_so),
	.X	(o_152)
    ) ;

    // Output pad for o_153 (rom_addr[8])
    MEM_OUT o_153_pad(
	.OT	(o_153_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_152_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_153_so),
	.X	(o_153)
    ) ;

    // Dummy pad vdd2_154 ()
    // vdd

    // Dummy pad vss2_155 ()
    // vss

    // Output pad for o_156 (rom_addr[9])
    MEM_OUT o_156_pad(
	.OT	(o_156_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_153_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_156_so),
	.X	(o_156)
    ) ;

    // Output pad for o_157 (rom_addr[10])
    MEM_OUT o_157_pad(
	.OT	(o_157_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_156_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_157_so),
	.X	(o_157)
    ) ;

    // Output pad for o_158 (rom_addr[11])
    MEM_OUT o_158_pad(
	.OT	(o_158_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_157_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_158_so),
	.X	(o_158)
    ) ;

    // Output pad for o_159 (rom_addr[12])
    MEM_OUT o_159_pad(
	.OT	(o_159_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_158_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_159_so),
	.X	(o_159)
    ) ;

    // Output pad for o_160 (rom_addr[13])
    MEM_OUT o_160_pad(
	.OT	(o_160_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_159_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_160_so),
	.X	(o_160)
    ) ;

    // Output pad for o_161 (rom_addr[14])
    MEM_OUT o_161_pad(
	.OT	(o_161_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_160_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_161_so),
	.X	(o_161)
    ) ;

    // Dummy pad vdd_162 ()
    // vdd

    // Output pad for o_163 (rom_addr[15])
    MEM_OUT o_163_pad(
	.OT	(o_163_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_161_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_163_so),
	.X	(o_163)
    ) ;

    // Output pad for o_164 (rom_addr[16])
    MEM_OUT o_164_pad(
	.OT	(o_164_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_163_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(o_164_so),
	.X	(o_164)
    ) ;

    // Output pad for o_165 (rom_addr[17])
    MEM_OUT o_165_pad(
	.OT	(o_165_o),
	.TN	(w_input_tn),
	.SHIFT	(bscan_shift),
	.SI	(o_164_so),
	.CK	(bscan_clk_cap),
	.UP	(bscan_clk_upd),
	.MD	(bscan_sel_ff_out),
	.SO	(scan_out),
	.X	(o_165)
    ) ;

    // Dummy pad vss_166 ()
    // vss


endmodule