/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)BSCN.v
***
****************************************************************************
****************************************************************************/
![[Up: MEM_IN_PD mem_scn2]](v2html-up.gif)
module BSCN2
(DINPN,
MODE,
SHIFT,
ENB,
UPDATE,
TDI,
SETN,
TDO,
DOUT);
input DINPN;
input MODE;
input SHIFT;
input ENB;
input UPDATE;
input TDI;
input SETN;
output TDO;
output DOUT;
wire latchq;
// DINPN is actually active high data
wire DOUT = MODE ? latchq : DINPN;
wire mux2_out = SHIFT ? TDI : DOUT;
Mflipflop capture_flop (TDO, mux2_out, ENB, 1'b0);
UDP_LATCH update_latch (latchq, ~UPDATE, TDO);
endmodule
module BSCN3 (DINP0N,
DINP1,
MODE0,
MODE1,
SHIFT,
ENB,
UPDATE,
TDI0,
TDI1,
SETN,
TDO0,
TDO1,
DOUT0,
DOUT1);
input DINP0N;
input DINP1;
input MODE0;
input MODE1;
input SHIFT;
input ENB;
input UPDATE;
input TDI0;
input TDI1;
input SETN;
output TDO0;
output TDO1;
output DOUT0;
output DOUT1;
wire flopout0, latchq0;
wire DOUT0N = MODE0 ? ~latchq0 : DINP0N;
wire DOUT0 = ~DOUT0N;
wire mux2_out = SHIFT ? TDI0 : DOUT0;
Mflipflop capture_flop0 (TDO0, mux2_out, ENB, 1'b0);
UDP_LATCH update_latch0 (latchq0, ~UPDATE, ~TDO0);
wire mux3_out = SHIFT ? TDI1 : DINP1;
wire latchq1;
Mflipflop capture_flop1 (TDO1, mux3_out, ENB, 1'b0);
UDP_LATCH update_latch1 (latchq1, ~UPDATE, TDO1);
wire DOUT1 = MODE1 ? latchq1 : DINP1;
endmodule
module BSCN4 (DINP,
MODE,
SHIFT,
ENB,
UPDATE,
TDI,
SETN,
TDO,
DOUT);
input DINP;
input MODE;
input SHIFT;
input ENB;
input UPDATE;
input TDI;
input SETN;
output TDO;
output DOUT;
wire latchq;
wire TDO;
wire DOUT = MODE ? latchq : DINP;
wire mux2_out = SHIFT ? TDI : DINP;
Mflipflop capture_flop (TDO, mux2_out, ENB, 1'b0);
UDP_LATCH update_latch (latchq, ~UPDATE, TDO);
endmodule
// Modified to include TN, PI and PO
... (truncated)
module PCI_BI (ENC_, OT, TN, PI, PO, SHIFT, SI, CK, UP, MD1,
MD2, SO, IT, X);
input ENC_; // tri_state enable, active low from BSCN4 output
input OT; // data to pad from core
input TN; // comes in from ssparc.v
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // load the jtag_flop
input UP; // update signal
input MD1; // output mode select, 0 = drive to pad data
input MD2; // input mode select, 0 = pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire bscn3_tdo0; // internal scan connection
wire bscn3_dout0; // jtag to output predriver
wire bscn3_dout1; // jtag to input (from input predriver)
// BAD NEWS, the signal to drive to the pad is active LOW!
wire bidi_in;
BSCN3 pci_bidi_scn3( .DINP0N (~bidi_in),
.DINP1 (OT),
.MODE0 (MD1),
.MODE1 (MD2),
.ENB (CK),
.SHIFT (SHIFT),
.UPDATE (UP),
.TDI0 (SI ),
.TDI1 (bscn3_tdo0),
.DOUT0 (IT),
.DOUT1 (bscn3_dout1),
.TDO0 (bscn3_tdo0),
.TDO1 (SO)
);
// Removed RBDEPCIF to RBDEPCI5F
//RBDEPCIF pci_bidi_slot(
RBDEPCI5F pci_bidi_slot(
.A (bscn3_dout1),
//.TN (1'b1),
.TN (TN),
.IO (X),
.PI (PI),
.PO (PO),
.EN (ENC_),
.ZI (bidi_in)
);
endmodule
module PCI_BI_OD (ENC_, OT, TN, PI, PO, SHIFT, SI, CK, UP, MD1,
MD2, SO, IT, X);
input ENC_; // tri_state enable, active low from BSCN4 output
input OT; // data to pad from core
input TN; // comes in from ssparc.v
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // load the jtag_flop
input UP; // update signal
input MD1; // output mode select, 0 = drive to pad data
input MD2; // input mode select, 0 = pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire bscn3_tdo0; // internal scan connection
wire bscn3_dout0; // jtag to output predriver
wire bscn3_dout1; // jtag to input (from input predriver)
// BAD NEWS, the signal to drive to the pad is active LOW!
wire bidi_in;
BSCN3 pci_bidi_scn3( .DINP0N (~bidi_in),
.DINP1 (OT),
.MODE0 (MD1),
.MODE1 (MD2),
.ENB (CK),
.SHIFT (SHIFT),
.UPDATE (UP),
.TDI0 (SI ),
.TDI1 (bscn3_tdo0),
.DOUT0 (IT),
.DOUT1 (bscn3_dout1),
.TDO0 (bscn3_tdo0),
.TDO1 (SO)
);
// Removed RBDEPCIF to RBDEPCI5F
//RBDEPCIF pci_bidi_slot(
RBDEPCI5F pci_bidi_slot(
.A (1'b0),
//.TN (1'b1),
.TN (TN),
.IO (X),
.PI (PI),
.PO (PO),
.EN (ENC_),
.ZI (bidi_in)
);
endmodule
// Modified to include TN
module MEM_BI (ENC_, OT, TN, PI, PO, SHIFT, SI, CK, UP, MD1,
MD2, SO, IT, X);
input ENC_; // tri_state enable, active low from BSCN4 output
input OT; // data to pad from core
input TN; // comes in from ssparc.v
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // load the jtag_flop
input UP; // update signal
input MD1; // output mode select, 0 = drive to pad data
input MD2; // input mode select, 0 = pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire bscn3_tdo0; // internal scan connection
wire bscn3_dout0; // jtag to output predriver
wire bscn3_dout1; // jtag to input (from input predriver)
wire bidi_in;
BSCN3 mem_bidi_scn3( .DINP0N (preibuf_z),
.DINP1 (OT),
.MODE0 (MD1),
.MODE1 (MD2),
.ENB (CK),
.SHIFT (SHIFT),
.UPDATE (UP),
.TDI0 (SI ),
.TDI1 (bscn3_tdo0),
.DOUT0 (IT),
.DOUT1 (bscn3_dout1),
.TDO0 (bscn3_tdo0),
.TDO1 (SO)
);
// keep the name pci_bidi_slot even though switch to mem
// so ssparc_chipdumpvars doesn't change. JP
BD6FDR pci_bidi_slot(
.A (bscn3_dout1),
.TN (TN),
.IO (X),
.EN (ENC_),
.Z (bidi_in)
);
PREIBUFNF mem_in_prein(
.A (bidi_in),
.PI (PI),
.PO (PO),
.Z (preibuf_z)
);
endmodule
/* DELETE this since not used use the above version JP
module MEM_BI (ENC_, OT, TN, SHIFT, SI, CK, UP, MD1,
MD2, SO, IT, X);
input ENC_; // tri_state enable, active low from BSCN4 output
input OT; // data to pad from core
input TN;
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // jtag_ff clock (gated in jtag controller)
input UP; // update signal
input MD1; // output mode select, 0 = drive to pad data
input MD2; // input mode select, 0 = pad data
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire bscn3_tdo0; // internal scan connection
wire bscn3_dout0; // jtag to output predriver
wire bscn3_dout1; // jtag to input (from input predriver)
wire bidi_in; // output of slot driver to prebuf
BSCN3 afx_bidi_scn3( .DINP0N (~bidi_in),
.DINP1 (OT),
.MODE0 (MD1),
.MODE1 (MD2),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI0 (SI ),
.TDI1 (bscn3_tdo0),
.DOUT0 (IT),
.DOUT1 (bscn3_dout1),
.TDO0 (bscn3_tdo0),
.TDO1 (SO)
);
BD6FDR afx_bidi_slot(
.A (bscn3_dout1),
.EN (ENC_),
//.TN (1'b1),
.TN (TN),
.IO (X),
.Z (bidi_in)
);
endmodule
*/
// Modified to include PI and PO
module MEM_IN (SHIFT, SI, CK, UP, MD, PI, PO,
SO, IT, X);
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // clock for jtag_ff
input UP; // update signal
input MD; // output mode select, 0 = drive to pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire preibuf_z;
// cell is inverting
BSCN2 mem_scn2( .DINPN (preibuf_z),
.MODE (MD),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI (SI),
.DOUT (IT),
.TDO (SO),
.SETN (1'b1)
);
wire ibuf_z;
IBUFFDR mem_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF mem_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (preibuf_z)
);
endmodule
// Modified to include TN
... (truncated)
module MEM_OUT (OT, TN, SHIFT, SI, UP, CK,
MD, SO, X);
input OT; // data to pad from core
input TN;
input SHIFT; // jtag_ff select
input SI; // scan-in data
input UP; // update signal
input CK; // clock for jtag ff
input MD; // input mode select, 0 = pad data
output SO; // scan-out
inout X; // actual pad data;
wire bscn4_dout; // jtag to output predriver
BSCN4 mem_out_scn4( .DINP (OT),
.MODE (MD),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI (SI ),
.DOUT (bscn4_dout),
.TDO (SO)
);
BD6FDR mem_out_slot(
.A (bscn4_dout),
//.TN (1'b1),
.TN (TN),
.EN (1'b0),
.IO (X)
);
endmodule
// Added PI and PO ports
module MEM_IN_NS_PU (IT, PI, PO, X);
output IT; // data to core
inout X; // actual pad data;
input PI;
output PO;
// cell has a pull up and is 5 v tolerant
IBUFPUFDR afx_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF afx_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (IT)
);
endmodule
// Added PI and PO ports
module TEST_IN (IT, X, PI, PO);
output IT; // data to core
inout X; // actual pad data;
input PI;
output PO;
// cell has a pull up and is 5 v tolerant
IIDDTNFDR iiddtndr ( .A (X),
.Z (pre_in)
);
PREIIDDTN preiiddtn (.IDDTN (IT),
.A (pre_in),
//.PI (1'b1)
.PI (PI),
.PO (PO)
);
endmodule
// Added PI and PO ports
module MEM_IN_NS_PD (IT, X, PI, PO);
output IT; // data to core
inout X; // actual pad data;
input PI;
output PO;
// cell has a pull down and is 5 v tolerant
IBUFPDFDR afx_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF afx_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (IT)
);
endmodule
module ENABLE (EN, SHIFT, SI, UP, CK,
MD, SO, ENC_);
input EN; // data to enable from core
input SHIFT; // jtag_ff select
input SI; // scan-in data
input UP; // update signal
input CK; // enb for jtag ff
input MD; // input mode select, 0 = pad data
output SO; // scan-out
output ENC_; // actual enable data;
wire ENC; // active high version
wire ENC_ = ~ENC; // active low version
BSCN4 afx_out_scn4( .DINP (EN),
.MODE (MD),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI (SI ),
.DOUT (ENC),
.TDO (SO)
);
endmodule
// Modified to include TN
module MEM_BI_NS (ENC_, OT, TN, X);
input ENC_; // tri_state enable, active low from BSCN4 output
input OT; // data to pad from core
input TN;
inout X; // actual pad data;
BD6FDR afx_bidi_slot(
.A (OT),
//.TN (1'b1),
.TN (TN),
.IO (X),
.EN (ENC_)
);
endmodule
// move in module PROCMON in place of TEST_OUT
//module TEST_OUT (ENC_, OT, X);
//input ENC_; // tri_state enable, active low from BSCN4 output
//input OT; // data to pad from core
//inout X; // actual pad data;
//PROC_DRV proc_drv(
//.A (OT),
//.Z (X),
//.EN (1'b1)
//);
//endmodule
module PROCMON ( Z, A, E, S, N, SCAN, SEL ) ;
input A, E, S, N, SCAN, SEL ;
output Z ;
// fix for release 1.0 JP
// add this wire
wire E_ = ~E;
//PROCMONA procmon_a ( z1, A, E, S, N );
PROCMONA procmon_a ( .Z(z1), .A(A), .E(E_), .S(S), .N(SCAN) );
//CSL_MUX21 procmon_mux ( mux_out, z1, SCAN, SEL ) ;
//MUX21HA procmon_mux ( mux_out, z1, SCAN, SEL ) ;
//PROC_DRV proc_driver ( Z, mux_out, S );
PROC_DRV proc_driver ( .Z(Z), .A(z1), .EN(S) );
endmodule
module POWER_IN ( X);
inout X; // actual pad data;
endmodule
// Modified to include TN
module MEM_OUT_NS (OT, TN, X);
input OT; // data to pad from core
input TN;
inout X; // actual pad data;
BD6FDR afx_out_slot(
.A (OT),
//.TN (1'b1),
.TN (TN),
.IO (X),
.EN (1'b0)
);
endmodule
module CLK_IN (IT,PO,PI,X);
output IT,PO; // data to core
input X,PI; // actual pad data;
wire IT;
wire ibuf_z, PO;
IBUFFDR mem_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF mem_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (IT)
);
/* Changed this for release 1.0 JP
// cell is inverting
CLKC8IDR afx_in_slot( .A (X),
.Z (ibuf_z)
);
// cell is inverting
PRECLKC8I afx_in_prein(
.A (ibuf_z),
.Z (IT)
);
*/
endmodule
module CLK_IN_PD (IT,PO,PI,X);
/* clk input with pulldown */
output IT,PO; // data to core
input X,PI; // actual pad data;
wire IT;
wire ibuf_z, PO;
IBUFPDFDR mem_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF mem_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (IT)
);
endmodule
// Added PI and PO ports
module MEM_IN_PU (SHIFT, SI, CK, UP, MD, PI, PO,
SO, IT, X);
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // clock for jtag_ff
input UP; // update signal
input MD; // output mode select, 0 = drive to pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire preibuf_z;
// cell is inverting
BSCN2 mem_scn2( .DINPN (preibuf_z),
.MODE (MD),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI (SI),
.DOUT (IT),
.TDO (SO),
.SETN (1'b1)
);
wire ibuf_z;
IBUFPUFDR mem_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF mem_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (preibuf_z)
);
endmodule
// Added PI and PO ports
module MEM_IN_PD (SHIFT, SI, CK, UP, MD, PI, PO,
SO, IT, X);
input SHIFT; // jtag_ff select
input SI; // scan-in data
input CK; // clock for jtag_ff
input UP; // update signal
input MD; // output mode select, 0 = drive to pad data
input PI;
output PO;
output SO; // scan-out
output IT; // data to core
inout X; // actual pad data;
wire preibuf_z;
// cell is inverting
BSCN2 mem_scn2( .DINPN (preibuf_z),
.MODE (MD),
.SHIFT (SHIFT),
.ENB (CK),
.UPDATE (UP),
.TDI (SI),
.DOUT (IT),
.TDO (SO),
.SETN (1'b1)
);
wire ibuf_z;
IBUFPDFDR mem_in_slot( .A (X),
.Z (ibuf_z)
);
PREIBUFF mem_in_prein(
.A (ibuf_z),
.PI (PI),
.PO (PO),
.Z (preibuf_z)
);
endmodule
| This page: |
Created: | Thu Aug 19 12:00:41 1999 |
| From: |
../../../sparc_v8/lib/rtl/BSCN.v
|