/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)botpads.v 1.21 11/03/97
// Automatically generated from iopad_order rev 1.9 by mkiopads, rev 1.9
![[Up: iopads botpads]](v2html-up.gif)
module botpads
( // Pads listed in left-to-right order:
// vss_84, // vss
cbeEnable, // cbeEnable
b_85, // cbe[3]
b_85_o,
b_85_i,
// vss_86, // vss
// vdd_87, // vdd
PAREnable, // PAREnable
b_88, // par
b_88_o,
b_88_i,
perrEn, // perrEn
b_89, // perr_l
b_89_o,
b_89_i,
serrEnable, // serrEnable
b_90, // serr_l
b_90_o,
b_90_i,
// vss_91, // vss
// vdd_92, // vdd
// change to open drain for 2.0
inta_oen, // inta_oen
b_93, // inta_
b_93_o,
b_93_i,
// change to open drain for 2.0
intb_oen, // intb_oen
b_94, // intb_
b_94_o,
b_94_i,
// change to open drain for 2.0
intc_oen, // intc_oen
b_95, // intc_
b_95_o,
b_95_i,
// change to open drain for 2.0
intd_oen, // intd_oen
b_96, // intd_
b_96_o,
b_96_i,
// vss2_97, // vss
// vdd2_98, // vdd
pci_rst_oen, // pci_rst_oen
o_99, // pci_rst_l
o_99_o,
o_99_i,
pci_clk3_oen, // pci_clk3_oen
b_100, // pci_clk3
b_100_o,
b_100_i,
jtag_tdo_oen_l, // jtag_tdo_oen_l, Active-low enable for jtag_tdo
t_ns_101, // jtag_tdo
t_ns_101_o,
// vss_102, // vss
// vdd_103, // vdd
i_ns_104, // jtag_trst_l
i_ns_104_i,
i_ns_105, // jtag_tdi
i_ns_105_i,
i_ns_106, // jtag_ms
i_ns_106_i,
i_ns_107, // jtag_ck
i_ns_107_i,
// vss_108, // vss
// vdd_109, // vdd
i_110, // bm_sel[0]
i_110_i,
i_111, // bm_sel[1]
i_111_i,
// vss2_112, // vss
i_113, // csl_scan_mode
i_113_i,
o_pm_114, // procmon
o_pm_114_e,
o_pm_114_s,
o_pm_114_n,
o_pm_114_csl_scan,
o_pm_114_sel,
o_pm_114_i,
// vdd2_115, // vdd
i_116, // ext_event_l
i_116_i,
i_117, // pll_byp_l
i_117_i,
// vss_118, // vss
// vdd_119, // vdd
i_clk_120, // ext_clk2
i_clk_120_i,
i_clk_121, // ext_clk1
i_clk_121_i,
i_ns_122, // pll_rst
i_ns_122_i,
pll_123, // pll_vdd
pll_123_i,
// vss2_124, // vss
// vdd2_125, // vdd
pll_126, // pll_vss
pll_126_i,
i_127, // sp_sel[2]
i_127_i,
i_128, // sp_sel[1]
i_128_i,
i_129, // sp_sel[0]
i_129_i,
// vss_130, // vss
// vdd_131, // vdd
o_132, // int_event_l
o_132_o,
// change the cp_stat_l[1:0] to 5,6th interrupt pins for 2.0
// o_133, // cp_stat_l[0]
// o_133_o,
// o_134, // cp_stat_l[1]
// o_134_o,
inte_oen,
b_133, // inte (open drain)
b_133_o,
b_133_i,
intf_oen,
b_134, // intf (open drain)
b_134_o,
b_134_i,
o_ns_135, // ref_clk
o_ns_135_o,
// change the standby pin to a 7'th interrupt pin for 2.0
// i_136, // standby
// i_136_i,
intg_oen,
b_136, // intg (open drain)
b_136_o,
b_136_i,
// change the spare pin at v16 to 8'th interrupt pin for 2.0
inth_oen,
b_136a, // inth (open drain)
b_136a_o,
b_136a_i,
i_137, // input_reset_l
i_137_i,
// vss_138, // vss
// vdd_139, // vdd
i_140, // div_ctl[1]
i_140_i,
i_141, // div_ctl[0]
i_141_i,
o_142, // rom_addr[0]
o_142_o,
o_143, // rom_addr[1]
o_143_o,
// vss_144, // vss
// vdd_145, // vdd
o_146, // rom_addr[2]
o_146_o,
o_147, // rom_addr[3]
o_147_o,
o_148, // rom_addr[4]
o_148_o,
o_149, // rom_addr[5]
o_149_o,
// vdd_150, // vdd
o_151, // rom_addr[6]
o_151_o,
o_152, // rom_addr[7]
o_152_o,
o_153, // rom_addr[8]
o_153_o,
// vdd2_154, // vdd
// vss2_155, // vss
o_156, // rom_addr[9]
o_156_o,
o_157, // rom_addr[10]
o_157_o,
o_158, // rom_addr[11]
o_158_o,
o_159, // rom_addr[12]
o_159_o,
o_160, // rom_addr[13]
o_160_o,
o_161, // rom_addr[14]
o_161_o,
// vdd_162, // vdd
o_163, // rom_addr[15]
o_163_o,
o_164, // rom_addr[16]
o_164_o,
o_165, // rom_addr[17]
o_165_o,
// vss_166, // vss
bscan_clk_cap,
bscan_clk_upd,
w_input_tn,
bscan_shift,
bscan_sel_ff_out,
bscan_sel_ff_in,
pi_in,
scan_in,
po_out,
scan_out
) ;
input cbeEnable ; // cbeEnable
inout b_85 ; // cbe[3]
input b_85_o ;
output b_85_i ;
input PAREnable ; // PAREnable
inout b_88 ; // par
input b_88_o ;
output b_88_i ;
input perrEn ; // perrEn
inout b_89 ; // perr_l
input b_89_o ;
output b_89_i ;
input serrEnable ; // serrEnable
inout b_90 ; // serr_l
input b_90_o ;
output b_90_i ;
input inta_oen ; // inta_oen
inout b_93 ; // inta_
input b_93_o ;
output b_93_i ;
input intb_oen ; // intb_oen
inout b_94 ; // intb_
input b_94_o ;
output b_94_i ;
input intc_oen ; // intc_oen
inout b_95 ; // intc_
input b_95_o ;
output b_95_i ;
input intd_oen ; // intd_oen
inout b_96 ; // intd_
input b_96_o ;
output b_96_i ;
input pci_rst_oen ; // pci_rst_oen
inout o_99 ; // pci_rst_l
input o_99_o ;
output o_99_i ;
input pci_clk3_oen ; // pci_clk3_oen
inout b_100 ; // pci_clk3
input b_100_o ;
output b_100_i ;
input jtag_tdo_oen_l ; // jtag_tdo_oen_l, Active-low enable for jtag_tdo
output t_ns_101 ; // jtag_tdo
input t_ns_101_o ;
input i_ns_104 ; // jtag_trst_l
output i_ns_104_i ;
input i_ns_105 ; // jtag_tdi
output i_ns_105_i ;
input i_ns_106 ; // jtag_ms
output i_ns_106_i ;
input i_ns_107 ; // jtag_ck
output i_ns_107_i ;
input i_110 ; // bm_sel[0]
output i_110_i ;
input i_111 ; // bm_sel[1]
output i_111_i ;
input i_113 ; // csl_scan_mode
output i_113_i ;
input o_pm_114 ; // procmon
input o_pm_114_e ;
input o_pm_114_s ;
input o_pm_114_n ;
input o_pm_114_csl_scan ;
input o_pm_114_sel ;
output o_pm_114_i ;
input i_116 ; // ext_event_l
output i_116_i ;
input i_117 ; // pll_byp_l
output i_117_i ;
input i_clk_120 ; // ext_clk2
output i_clk_120_i ;
input i_clk_121 ; // ext_clk1
output i_clk_121_i ;
input i_ns_122 ; // pll_rst
output i_ns_122_i ;
input pll_123 ; // pll_vdd
output pll_123_i ;
input pll_126 ; // pll_vss
output pll_126_i ;
input i_127 ; // sp_sel[2]
output i_127_i ;
input i_128 ; // sp_sel[1]
output i_128_i ;
input i_129 ; // sp_sel[0]
output i_129_i ;
output o_132 ; // int_event_l
input o_132_o ;
// change cp_stat[1:0] to open drain interrupts for 2.0
inout b_133 ; // inte
input b_133_o ;
output b_133_i ;
input inte_oen ;
inout b_134 ; // intf
input b_134_o ;
output b_134_i ;
input intf_oen ;
output o_ns_135 ; // ref_clk
input o_ns_135_o ;
// change standby to open drain interrupt
inout b_136 ; // intg
output b_136_i ;
input b_136_o ;
input intg_oen ;
// change spare at v16 to open drain interrupt
inout b_136a ; // inth
output b_136a_i ;
input b_136a_o ;
input inth_oen ;
input i_137 ; // input_reset_l
output i_137_i ;
input i_140 ; // div_ctl[1]
output i_140_i ;
input i_141 ; // div_ctl[0]
output i_141_i ;
output o_142 ; // rom_addr[0]
input o_142_o ;
output o_143 ; // rom_addr[1]
input o_143_o ;
output o_146 ; // rom_addr[2]
input o_146_o ;
output o_147 ; // rom_addr[3]
input o_147_o ;
output o_148 ; // rom_addr[4]
input o_148_o ;
output o_149 ; // rom_addr[5]
input o_149_o ;
output o_151 ; // rom_addr[6]
input o_151_o ;
output o_152 ; // rom_addr[7]
input o_152_o ;
output o_153 ; // rom_addr[8]
input o_153_o ;
output o_156 ; // rom_addr[9]
input o_156_o ;
output o_157 ; // rom_addr[10]
input o_157_o ;
output o_158 ; // rom_addr[11]
input o_158_o ;
output o_159 ; // rom_addr[12]
input o_159_o ;
output o_160 ; // rom_addr[13]
input o_160_o ;
output o_161 ; // rom_addr[14]
input o_161_o ;
output o_163 ; // rom_addr[15]
input o_163_o ;
output o_164 ; // rom_addr[16]
input o_164_o ;
output o_165 ; // rom_addr[17]
input o_165_o ;
input bscan_clk_cap ;
input bscan_clk_upd ;
input w_input_tn ;
input bscan_shift ;
input bscan_sel_ff_out ;
input bscan_sel_ff_in ;
input pi_in ;
input scan_in ;
output po_out ;
output scan_out ;
// Dummy pad vss_84 ()
// vss
// Tristate enable cell for cbeEnable
ENABLE cbeEnable_cell(
.EN (cbeEnable),
.SHIFT (bscan_shift),
.SI (scan_in),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (cbeEnable_enc_l),
.SO (cbeEnable_so)
) ;
// Bidirectional pad for b_85 (cbe[3]), enabled by cbeEnable
PCI_BI b_85_pad(
.ENC_ (cbeEnable_enc_l),
.OT (b_85_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (cbeEnable_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (pi_in),
.PO (b_85_po),
.SO (b_85_so),
.IT (b_85_i),
.X (b_85)
) ;
// Dummy pad vss_86 ()
// vss
// Dummy pad vdd_87 ()
// vdd
// Tristate enable cell for PAREnable
ENABLE PAREnable_cell(
.EN (PAREnable),
.SHIFT (bscan_shift),
.SI (b_85_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (PAREnable_enc_l),
.SO (PAREnable_so)
) ;
// Bidirectional pad for b_88 (par), enabled by PAREnable
PCI_BI b_88_pad(
.ENC_ (PAREnable_enc_l),
.OT (b_88_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (PAREnable_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_85_po),
.PO (b_88_po),
.SO (b_88_so),
.IT (b_88_i),
.X (b_88)
) ;
// Tristate enable cell for perrEn
ENABLE perrEn_cell(
.EN (perrEn),
.SHIFT (bscan_shift),
.SI (b_88_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (perrEn_enc_l),
.SO (perrEn_so)
) ;
// Bidirectional pad for b_89 (perr_l), enabled by perrEn
PCI_BI b_89_pad(
.ENC_ (perrEn_enc_l),
.OT (b_89_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (perrEn_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_88_po),
.PO (b_89_po),
.SO (b_89_so),
.IT (b_89_i),
.X (b_89)
) ;
// Tristate enable cell for serrEnable
ENABLE serrEnable_cell(
.EN (serrEnable),
.SHIFT (bscan_shift),
.SI (b_89_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (serrEnable_enc_l),
.SO (serrEnable_so)
) ;
// Bidirectional pad for b_90 (serr_l), enabled by serrEnable
PCI_BI b_90_pad(
.ENC_ (serrEnable_enc_l),
.OT (b_90_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
// remove scan chain from open drain signal
// .SI (serrEnable_so),
.SI (1'b0),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_89_po),
.PO (b_90_po),
// .SO (b_90_so),
.SO ( ),
.IT (b_90_i),
.X (b_90)
) ;
// Dummy pad vss_91 ()
// vss
// Dummy pad vdd_92 ()
// vdd
// Tristate enable cell for inta_oen
ENABLE inta_oen_cell(
.EN (inta_oen),
.SHIFT (bscan_shift),
// .SI (b_90_so),
.SI (serrEnable_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (inta_oen_enc_l),
.SO (inta_oen_so)
) ;
// Bidirectional pad for b_93 (inta_), enabled by inta_oen
// changed to open drain for 2.0 so remove scan chain
PCI_BI b_93_pad(
.ENC_ (inta_oen_enc_l),
.OT (b_93_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
// .SI (inta_oen_so),
.SI (1'b0),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_90_po),
.PO (b_93_po),
// .SO (b_93_so),
.SO (),
.IT (b_93_i),
.X (b_93)
) ;
// Tristate enable cell for intb_oen
ENABLE intb_oen_cell(
.EN (intb_oen),
.SHIFT (bscan_shift),
// .SI (b_93_so),
.SI (inta_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (intb_oen_enc_l),
.SO (intb_oen_so)
) ;
// Bidirectional pad for b_94 (intb_), enabled by intb_oen
// changed to open drain for 2.0 so remove scan bit
PCI_BI b_94_pad(
.ENC_ (intb_oen_enc_l),
.OT (b_94_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
// .SI (intb_oen_so),
.SI (1'b0),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_93_po),
.PO (b_94_po),
// .SO (b_94_so),
.SO ( ),
.IT (b_94_i),
.X (b_94)
) ;
// Tristate enable cell for intc_oen
ENABLE intc_oen_cell(
.EN (intc_oen),
.SHIFT (bscan_shift),
// .SI (b_94_so),
.SI (intb_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (intc_oen_enc_l),
.SO (intc_oen_so)
) ;
// Bidirectional pad for b_95 (intc_), enabled by intc_oen
// changed to open drain for 2.0
PCI_BI b_95_pad(
.ENC_ (intc_oen_enc_l),
.OT (b_95_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
// .SI (intc_oen_so),
.SI (1'b0),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_94_po),
.PO (b_95_po),
// .SO (b_95_so),
.SO ( ),
.IT (b_95_i),
.X (b_95)
) ;
// Tristate enable cell for intd_oen
ENABLE intd_oen_cell(
.EN (intd_oen),
.SHIFT (bscan_shift),
// .SI (b_95_so),
.SI (intc_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (intd_oen_enc_l),
.SO (intd_oen_so)
) ;
// Bidirectional pad for b_96 (intd_), enabled by intd_oen
// change to open drain for 2.0
PCI_BI b_96_pad(
.ENC_ (intd_oen_enc_l),
.OT (b_96_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
// .SI (intd_oen_so),
.SI (1'b0),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_95_po),
.PO (b_96_po),
// .SO (b_96_so),
.SO ( ),
.IT (b_96_i),
.X (b_96)
) ;
// Dummy pad vss2_97 ()
// vss
// Dummy pad vdd2_98 ()
// vdd
// Tristate enable cell for pci_rst_oen
ENABLE pci_rst_oen_cell(
.EN (pci_rst_oen),
.SHIFT (bscan_shift),
// .SI (b_96_so),
.SI (intd_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_rst_oen_enc_l),
.SO (pci_rst_oen_so)
) ;
// Bidirectional pad for o_99 (pci_rst_l), enabled by pci_rst_oen
PCI_BI o_99_pad(
.ENC_ (pci_rst_oen_enc_l),
.OT (o_99_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_rst_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (b_96_po),
.PO (o_99_po),
.SO (o_99_so),
.IT (o_99_i),
.X (o_99)
) ;
// Tristate enable cell for pci_clk3_oen
ENABLE pci_clk3_oen_cell(
.EN (pci_clk3_oen),
.SHIFT (bscan_shift),
.SI (o_99_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.ENC_ (pci_clk3_oen_enc_l),
.SO (pci_clk3_oen_so)
) ;
// Bidirectional pad for b_100 (pci_clk3), enabled by pci_clk3_oen
PCI_BI b_100_pad(
.ENC_ (pci_clk3_oen_enc_l),
.OT (b_100_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (pci_clk3_oen_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD1 (bscan_sel_ff_out),
.MD2 (bscan_sel_ff_in),
.PI (o_99_po),
.PO (b_100_po),
.SO (b_100_so),
.IT (b_100_i),
.X (b_100)
) ;
// Dummy pad jtag_tdo_oen_l (jtag_tdo_oen_l)
// Active-low enable for jtag_tdo
// Non-scanned tristated output pad for t_ns_101 (jtag_tdo), enabled by jtag_tdo_oen_l
MEM_BI_NS t_ns_101_pad(
.ENC_ (jtag_tdo_oen_l),
.OT (t_ns_101_o),
// .TN (w_input_tn),
.TN (1'b1),
.X (t_ns_101)
) ;
// Dummy pad vss_102 ()
// vss
// Dummy pad vdd_103 ()
// vdd
// Non-scanned input pad for i_ns_104 (jtag_trst_l)
// MEM_IN_NS_PU i_ns_104_pad(
// change to pull down for 2.0
// MEM_IN_NS_PD i_ns_104_pad(
// change back to pull up for 2.1 (according to jtag spec)
MEM_IN_NS_PU i_ns_104_pad(
.X (i_ns_104),
.PI (b_100_po),
.PO (i_ns_104_po),
.IT (i_ns_104_i)
) ;
// Non-scanned input pad for i_ns_105 (jtag_tdi)
MEM_IN_NS_PU i_ns_105_pad(
.X (i_ns_105),
.PI (i_ns_104_po),
.PO (i_ns_105_po),
.IT (i_ns_105_i)
) ;
// Non-scanned input pad for i_ns_106 (jtag_ms)
MEM_IN_NS_PU i_ns_106_pad(
.X (i_ns_106),
.PI (i_ns_105_po),
.PO (i_ns_106_po),
.IT (i_ns_106_i)
) ;
// Non-scanned input pad for i_ns_107 (jtag_ck)
MEM_IN_NS_PU i_ns_107_pad(
.X (i_ns_107),
.PI (i_ns_106_po),
.PO (i_ns_107_po),
.IT (i_ns_107_i)
) ;
// Dummy pad vss_108 ()
// vss
// Dummy pad vdd_109 ()
// vdd
// Input pad for i_110 (bm_sel[0])
MEM_IN_PD i_110_pad(
.X (i_110),
.SHIFT (bscan_shift),
.SI (b_100_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_ns_107_po),
.PO (i_110_po),
.SO (i_110_so),
.IT (i_110_i)
) ;
// Input pad for i_111 (bm_sel[1])
MEM_IN_PD i_111_pad(
.X (i_111),
.SHIFT (bscan_shift),
.SI (i_110_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_110_po),
.PO (i_111_po),
.SO (i_111_so),
.IT (i_111_i)
) ;
// Dummy pad vss2_112 ()
// vss
// Non-scanned input pad for i_113 (csl_scan_mode)
MEM_IN_NS_PD i_113_pad(
.X (i_113),
// disconnect nand tree from csl_scan_mode
.PI (1'b1),
.PO ( ),
.IT (i_113_i)
) ;
// Non-scanned input pad for o_pm_114 (procmon)
PROCMON o_pm_114_pad(
.A (o_pm_114),
.E (o_pm_114_e),
.S (o_pm_114_s),
.N (o_pm_114_n),
.SCAN (o_pm_114_csl_scan),
.SEL (o_pm_114_sel),
.Z (o_pm_114_i)
) ;
// Dummy pad vdd2_115 ()
// vdd
// Input pad for i_116 (ext_event_l)
MEM_IN i_116_pad(
.X (i_116),
.SHIFT (bscan_shift),
.SI (i_111_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_111_po),
.PO (i_116_po),
.SO (i_116_so),
.IT (i_116_i)
) ;
// Non-scanned input pad for i_117 (pll_byp_l)
MEM_IN_NS_PU i_117_pad(
.X (i_117),
.PI (i_116_po),
.PO (i_117_po),
.IT (i_117_i)
) ;
// Dummy pad vss_118 ()
// vss
// Dummy pad vdd_119 ()
// vdd
// Non-scanned input pad for i_clk_120 (ext_clk2)
// change to have a pull down on version 2.0 (potentially used as slave mode)
// CLK_IN i_clk_120_pad(
CLK_IN_PD i_clk_120_pad(
// Add pi, po with swithc to ibuf for release 1.0
.PI (i_117_po),
.PO (i_clk_120_po),
.X (i_clk_120),
.IT (i_clk_120_i)
) ;
// Non-scanned input pad for i_clk_121 (ext_clk1)
CLK_IN i_clk_121_pad(
// Add pi, po with swithc to ibuf for release 1.0
.PI (i_clk_120_po),
.PO (i_clk_121_po),
.X (i_clk_121),
.IT (i_clk_121_i)
) ;
// Non-scanned input pad for i_ns_122 (pll_rst)
// MEM_IN_NS_PD i_ns_122_pad(
// change to pullup for 2.0
MEM_IN_NS_PU i_ns_122_pad(
.X (i_ns_122),
.PI (i_clk_121_po),
.PO (i_ns_122_po),
.IT (i_ns_122_i)
) ;
// Non-scanned input pad for pll_123 (pll_vdd)
PLLVDD pll_123_pad(
.A (pll_123),
.Z (pll_123_i)
) ;
// Dummy pad vss2_124 ()
// vss
// Dummy pad vdd2_125 ()
// vdd
// Non-scanned input pad for pll_126 (pll_vss)
PLLVSS pll_126_pad(
.A (pll_126),
.Z (pll_126_i)
) ;
// Input pad for i_127 (sp_sel[2])
MEM_IN_PD i_127_pad(
.X (i_127),
.SHIFT (bscan_shift),
.SI (i_116_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_ns_122_po),
.PO (i_127_po),
.SO (i_127_so),
.IT (i_127_i)
) ;
// Input pad for i_128 (sp_sel[1])
MEM_IN_PD i_128_pad(
.X (i_128),
.SHIFT (bscan_shift),
.SI (i_127_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_127_po),
.PO (i_128_po),
.SO (i_128_so),
.IT (i_128_i)
) ;
// Input pad for i_129 (sp_sel[0])
MEM_IN_PD i_129_pad(
.X (i_129),
.SHIFT (bscan_shift),
.SI (i_128_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_in),
.PI (i_128_po),
.PO (i_129_po),
.SO (i_129_so),
.IT (i_129_i)
) ;
// Dummy pad vss_130 ()
// vss
// Dummy pad vdd_131 ()
// vdd
// Output pad for o_132 (int_event_l)
MEM_OUT o_132_pad(
.OT (o_132_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (i_129_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_132_so),
.X (o_132)
) ;
/* delete this and change to open drain pci bi for 2.0
// Output pad for o_133 (cp_stat_l[0])
MEM_OUT o_133_pad(
.OT (o_133_o),
.TN (w_input_tn),
.SHIFT (bscan_shift),
.SI (o_132_so),
.CK (bscan_clk_cap),
.UP (bscan_clk_upd),
.MD (bscan_sel_ff_out),
.SO (o_133_so),
.X (o_133)
) ;
*/
| This page: |
Created: | Thu Aug 19 11:57:40 1999 |
| From: |
../../../sparc_v8/ssparc/iopads/rtl/botpads.v
|