/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)config_addr.v
***
***  Description:
***    Implements the configuration address reg.
*** 
****************************************************************************
****************************************************************************/


module config_addr(	
		reset,			// reset
		clock,			// clock
		data_in,		// data in -even word only!
		load_config_add,	// load address 

		special_cycle_decode,	// special cycle decode
					// converts config data writes to						// special cycle
		config_add_31,		// config_data control bit
		config_add,		// config address for afx reads
 		config_add_pci);	// config add to pci bus

// This module contains the configuration address and decoding to provide
// the appropriate type 0 or type 1 configuration for pci.  The configuration
// address register is also decoded to determine if a special cycle will
// be generated from a config data write.

input 		reset;
input		clock;
input	[31:0]  data_in;
input		load_config_add;

output		special_cycle_decode;
output		config_add_31;
output  [31:0]  config_add;
output  [31:0]  config_add_pci;

reg	[31:0]	config_add;

// originally assumed that the config address had to be modified to
// generate the type 0 or type 1 configuration messages.  This is
// done in the core!

//wire [31:0] type1_add = {8'h00,config_add[23:0]};
//wire [31:0] type0_add = {decode5to21(config_add[15:11]),config_add[10:0]};

wire [31:0] config_add_pci = config_add;

wire config_add_31 = config_add[31];

wire special_cycle_decode = (config_add[15:8] == 8'hff) & 
	(config_add[7:2] == 6'h00); 

always @(posedge clock)
begin
  if(reset)
    config_add <= 32'h00000000;

  else if(load_config_add )
    config_add <= #1 data_in;
end

/*		don't need this!!
function [21:0] decode5to21;
input [4:0] device_number;
begin
casex(device_number)
  5'b00000:	decode5to21 = 21'h000000;
  5'b00001:	decode5to21 = 21'h000001;
  5'b00010:	decode5to21 = 21'h000002;
  5'b00011:	decode5to21 = 21'h000004;
  5'b00100:	decode5to21 = 21'h000008;
  5'b00101:	decode5to21 = 21'h000010;
  5'b00110:	decode5to21 = 21'h000020;
  5'b00111:	decode5to21 = 21'h000040;
  5'b01000:	decode5to21 = 21'h000080;
  5'b01001:	decode5to21 = 21'h000100;
  5'b01010:	decode5to21 = 21'h000200;
  5'b01011:	decode5to21 = 21'h000400;
  5'b01100:	decode5to21 = 21'h000800;
  5'b01101:	decode5to21 = 21'h001000;
  5'b01110:	decode5to21 = 21'h002000;
  5'b01111:	decode5to21 = 21'h004000;
  5'b10000:	decode5to21 = 21'h008000;
  5'b10001:	decode5to21 = 21'h010000;
  5'b10010:	decode5to21 = 21'h020000;
  5'b10011:	decode5to21 = 21'h040000;
  5'b10100:	decode5to21 = 21'h080000;
  5'b10101:	decode5to21 = 21'h100000;
  default:	decode5to21 = 21'h000000;
endcase
end

endfunction

*/

endmodule