/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)cregloadctl.v 1.1 4/7/92
//
module CregLoadCtl
(
// inputs
RomCregCtl,
QuoBits,
notAbortWB,
SNnotDB,
CregSNBits,
// outputs
InForCreg,
InForCregDB,
RomFracBSL2FromC,
FracCregLoadCtl0,
FracCregLoadEn);
input [`end_frac_creg_field:`start_frac_creg_field] RomCregCtl
;
input [1:0] QuoBits
;
input [1:0] CregSNBits
;
input notAbortWB
,
SNnotDB
;
output [1:0] InForCreg
, InForCregDB
;
output RomFracBSL2FromC
;
output FracCregLoadCtl0
,
FracCregLoadEn
;
wire [1:0] InForCregSN
;
/* *********************************************************
Control Logic For Creg
********************************************************* */
ME_INVA g100 (SNnotDB, DBnotSN
);
ME_AND2 fg1s (QuoBits[1], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[1]);
ME_AND2 fg0s (QuoBits[0], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[0]);
ME_AND3 fg1d (QuoBits[1], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[1]);
ME_AND3 fg0d (QuoBits[0], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[0]);
ME_MUX2B fg1 (SNnotDB, CregSNBits[1], InForCregSN[1], InForCreg[1]);
ME_MUX2B fg0 (SNnotDB, CregSNBits[0], InForCregSN[0], InForCreg[0]);
ME_INVA fg9s (RomCregCtl[`u_FracCregFromFunc0], notResultOrQuoBits
);
ME_AND2 icr9 (RomCregCtl[`u_FracCregFromFunc1], notResultOrQuoBits,
RomFracBSL2FromC); // 1 0 ie SQRT
ME_INVA fgg (notAbortWB, AbortWB
);
ME_NOR2 icr (RomCregCtl[`u_FracCregFromFunc0],
RomCregCtl[`u_FracCregFromFunc1],
notEn
);
ME_NOR2 rct (notEn,
AbortWB,
FracCregLoadEn);
/* Feedthroughs */
ME_BUFF g00 (RomCregCtl[`u_FracCregFromFunc1], FracCregLoadCtl0);
endmodule
This page: |
Created: | Thu Aug 19 12:00:14 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/cregloadctl.v
|