/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)frac_ctl.v 1.1 4/7/92
//
// Top-level interconnect module for the fraction datapath control modules.
//
// This interconnect module was produced by Synopsys grouping and then edited
// by hand to remove hierarchy from signal names and make
// things more readable..
module frac_ctl
( Phi, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
FracBregSign, FracSign, LoadForInt, LoadOprs, notAbortWB,
notAM31_3, notAM2_0, notAregMasterFPMSBP1, notSticky1,
PreventSwap, Rom_Inexact, RomShForAlign, SNnotDB, SROneMore,
SRToSticky, StickyForSR1, AregMaster_57_40,
AregMaster_7_0,
CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn, notMultip, notSticky4,
Rom_63_48, SALSBs, SBLSBs, SCLSBs, SRControl, StepRemBits, Sticky2,
StickyExtra, SumInLSBs, TregLSBs, YDest,
CarryOut0, CarryOut3, FracAregLoadEn, FracBregLoadEn,
FracCregLoadEn, FracCregLC, FracTregLoadEn, Inexact,
InitialCarryBit, InitialMulStep, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notStickyInForSR,
SumCarryLoadEn, SumOut0, FracAregLC, FracBregLC, FracYbusLSBs,
InForCreg, InForCregDB, InFromCregOr0, LIB, notNO, notsh, Pos, Shift,
TopBitsIn, Zero );
input Phi
, AregMaster_32
, BregFPMSBM1
, CALSB
, CBLSB
, CCLSB
,
FracBregSign
, FracSign
, LoadForInt
, LoadOprs
, notAbortWB
,
notAM31_3
, notAM2_0
, notAregMasterFPMSBP1
, notSticky1
,
PreventSwap
, Rom_Inexact
, RomShForAlign
, SNnotDB
, SROneMore
,
SRToSticky
, StickyForSR1
;
input [57:40] AregMaster_57_40
;
input [7:0] AregMaster_7_0
;
input [2:0] CarryInLSBs
;
input [1:0] CregInSL2SQRT
;
input [1:0] CregSNBits
;
input [8:0] ExpIn
;
input [8:0] notMultip
;
input [3:0] notSticky4
;
input [63:48] Rom_63_48
;
input [1:0] SALSBs
;
input [1:0] SBLSBs
;
input [1:0] SCLSBs
;
input [3:0] SRControl
;
input [3:0] StepRemBits
;
input [1:0] Sticky2
;
input [1:0] StickyExtra
;
input [2:0] SumInLSBs
;
input [1:0] TregLSBs
;
input [6:0] YDest
;
output CarryOut0
, CarryOut3
, FracAregLoadEn
, FracBregLoadEn
,
FracCregLoadEn
, FracCregLC
, FracTregLoadEn
, Inexact
,
InitialCarryBit
, InitialMulStep
, notFracYFromD1A
,
notFracYFromD2A
, notFracYFromD3A
, notStickyInForSR
,
SumCarryLoadEn
, SumOut0
;
output [2:0] FracAregLC
;
output [2:0] FracBregLC
;
output [1:0] FracYbusLSBs
;
output [1:0] InForCreg
;
output [1:0] InForCregDB
;
output [1:0] InFromCregOr0
;
output [2:0] LIB
;
output [1:0] notNO
;
output [3:1] notsh
;
output [3:0] Pos
;
output [3:0] Shift
;
output [8:0] TopBitsIn
;
output [3:0] Zero
;
wire LoadFromMult
, RomFracBSL2FromC
, SelInitRemBits
;
wire [3:1] DivMultiple
;
wire [1:0] QuoBits
;
BregLoadCtl fblc ( .RomFracBregLC( Rom_63_48[60:59] ), .RomBSL2InFromC(
RomFracBSL2FromC), .LoadOprs(LoadOprs), .notAbortWB(notAbortWB),
.PreventSwap(PreventSwap), .LoadFromMult(LoadFromMult), .CregInSL2SQRT(
CregInSL2SQRT[1:0] ), .FracBregLC( FracBregLC[2:0] ), .FracBregLoadEn(
FracBregLoadEn), .InFromCregOr0( InFromCregOr0[1:0] ) );
ShiftLeftCtl slc ( .NI_49_47( AregMaster_57_40[49:47] ), .LoadForInt(
LoadForInt), .LIB( LIB[2:0] ) );
AregLoadCtl falc ( .ROM( Rom_63_48[58:56] ), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap), .FracAregLC(
FracAregLC[2:0] ), .FracAregLoadEn(FracAregLoadEn), .LoadFromMult(
LoadFromMult), .SelInitRemBits(SelInitRemBits) );
TregLoadCtl tlc ( .RomFracTFromRes(Rom_63_48[63] ),
.notAbortWB(notAbortWB), .FracTregLoadEn(FracTregLoadEn) );
NormCalSlice an ( .NI( AregMaster_57_40[55:40] ), .notsh( notsh[3:1] ),
.notNO( notNO[1:0] ) );
AregInexact aic ( .RomInexactRound(Rom_Inexact), .SNnotDB(SNnotDB),
.AMCBit(AregMaster_57_40[56] ), .AM32(AregMaster_32), .AM3(
AregMaster_7_0[3] ), .notAM31_3(notAM31_3), .notAM2_0(notAM2_0),
.Inexact(Inexact) );
MultiplierLSB mlsb ( .Rom_ResetMul(Rom_63_48[63] ), .notMultip(
notMultip[8:0] ), .notAbortWB(notAbortWB), .SumInLSBs(SumInLSBs[2:0] ),
.CarryInLSBs( CarryInLSBs[2:0] ), .SCLSBs( SCLSBs[1:0] ), .SBLSBs(
SBLSBs[1:0] ), .SALSBs( SALSBs[1:0] ), .CCLSB(CCLSB), .CBLSB(CBLSB),
.CALSB(CALSB), .Shift( Shift[3:0] ), .Pos( Pos[3:0] ), .Zero(
Zero[3:0] ), .CarryOut0(CarryOut0), .CarryOut3(CarryOut3), .SumOut0(
SumOut0), .SumCarryLoadEn(SumCarryLoadEn), .InitialMulStep(
InitialMulStep), .InitialCarryBit(InitialCarryBit) );
DivLog divl ( .Phi(Phi), .AregFPMSBM1(AregMaster_57_40[54] ),
.BregFPMSBM1(BregFPMSBM1), .StepRemBits( StepRemBits[3:0] ),
.InitialRemBits( AregMaster_57_40[57:54] ), .SelectInitial(
SelInitRemBits), .FracSign(FracSign), .DivMultiple( DivMultiple[3:1] ),
.QuotientBits( QuoBits[1:0] ) );
CregLoadCtl fclc ( .RomCregCtl(Rom_63_48[62:61] ), .QuoBits(QuoBits[1:0] ),
.notAbortWB(notAbortWB), .SNnotDB(SNnotDB), .CregSNBits(
CregSNBits[1:0] ), .InForCreg( InForCreg[1:0] ), .InForCregDB(
InForCregDB[1:0] ), .RomFracBSL2FromC(RomFracBSL2FromC),
.FracCregLoadCtl0(FracCregLC), .FracCregLoadEn(FracCregLoadEn) );
ShiftRightCtl src ( .LoadForInt(LoadForInt), .AregMasterBuf_57_55(
AregMaster_57_40[57:55] ), .ExpIn( ExpIn[8:0] ), .SRControl(
SRControl[3:0] ), .SROneMore(SROneMore), .SRToStky(SRToSticky),
.Stky8( AregMaster_7_0[7:0] ), .notStky4( notSticky4[3:0] ),
.Stky2( Sticky2[1:0] ), .notStky1(notSticky1), .StkyExtra(
StickyExtra[1:0] ), .RomShForAl(RomShForAlign), .notStkyInForSR(
notStickyInForSR), .TopBitsIn( TopBitsIn[8:0] ) );
YMuxCtl fymc ( .RomYMuxCtl( Rom_63_48[55:48] ), .YFunc( YDest[6:0] ),
.FracAregFPMSBP1( AregMaster_57_40[56] ), .notFracAregFPMSBP1(
notAregMasterFPMSBP1), .FracBregSign(FracBregSign), .DivMultiple(
DivMultiple[3:1] ), .AregLSBs( AregMaster_7_0[2:0] ),
.StickyForSR1(StickyForSR1), .TregLSBs( TregLSBs[1:0] ),
.notFracYFromD1A(notFracYFromD1A), .notFracYFromD2A(notFracYFromD2A),
.notFracYFromD3A(notFracYFromD3A), .FracYLSBs( FracYbusLSBs[1:0] ) );
endmodule
This page: |
Created: | Thu Aug 19 12:00:34 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_ctl/rtl/frac_ctl.v
|