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/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 


module dtag_ram ( ain, din, dout, bw);
output [32:0] dout;
input [32:0] din,bw;
input [9:0] ain;

wire  [9:0]   t_ain =ain;
wire [18:0]   t_di = din[32:14];
wire          t_di_vb =din[13];
wire  [7:0]   t_di_cb =din[12:5];
wire  [4:0]   t_di_acc = din[4:0];
wire          t_we =bw[32];
wire          t_we_vb =bw[13];

wire  [18:0]  t_do;
assign dout[32:14] = t_do;
 
wire          t_do_vb ;
assign dout[13] = t_do_vb;

wire  [7:0]   t_do_cb ;
assign dout[12:5] = t_do_cb;

wire  [4:0]   t_do_acc ;
assign dout[4:0] = t_do_acc;

	// synopsys translate_off

	// Dtag ram instantiated, maxblocks = 1024 for HARRIER
    	reg [18:0] t_ram [0:1023] ;
    	reg t_v_ram [0:1023] ;
    	reg [4:0] t_acc_ram [0:1023] ;
    	reg [7:0] t_cntx_ram [0:1023] ;
	// In actual layout also these are shorted together.
  	wire t_we_cb = t_we;

	wire we_, we_vb_, we_cb_;
	assign we_	= ~t_we;
	assign we_vb_	= ~t_we_vb;
	assign we_cb_	= ~t_we_cb;

	// Dtag read
        assign t_do 	= we_ ? t_ram[t_ain]      : t_di;
	assign t_do_cb	= we_cb_ ? t_cntx_ram[t_ain] : t_di_cb;
	assign t_do_acc	= we_cb_ ? t_acc_ram[t_ain]  : t_di_acc;
	assign t_do_vb 	= we_vb_ ? t_v_ram[t_ain] : t_di_vb;

	// Write Dtag Virtual Address field 
	always @(negedge we_) t_ram[t_ain] = t_di;

	// Write Dtag Context & ACC fields
	always @(negedge we_cb_) begin
		t_cntx_ram[t_ain] = t_di_cb;
                t_acc_ram[t_ain]  = t_di_acc;
	end
	// Write Dtag Valid Bit
        always @(negedge we_vb_) t_v_ram[t_ain] = t_di_vb;
 
	// synopsys translate_on

endmodule