/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
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/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)mc_dtag.v 1.27 9/15/93
// I/D-Cache Tag Megacell model
module mc_dtag
(
mc_dtag_scan_in,
mc_dtag_scan_out,
ain_w, // Address in.
t_do, // Data out.
t_di, // Data in.
t_val_in, // Valid bit in.
t_val_out,
wle_w,
t_be,
t_be_vb,
t_be_cb,
power_down_w,
dc_iiddtn,
t_acc_in,
t_acc_out,
t_cntx_in,
t_cntx_out,
t_hit,
t_index3, // Page flush: (0,0,0), Seg flush : (0,0,1),
t_index2, // Reg flush : (0,1,1), Cntx flush: (1,1,1),
t_index1, // User flush: (1,1,1)
t_flush, // where triplet is (t_index1,t_index2,t_index3)
t_flush_user, // The meaning of t_flush was changed from:
t_flush_user_cntx, // positive to negative logic(BUG 161),since
t_at, // we did not want to change the megacell.
// (i.e. insert a inverter after t_flush)
t_scan_mode,
t_tg_strobe,
t_clk
) ;
input mc_dtag_scan_in
;
output mc_dtag_scan_out
;
input [8:0] ain_w
; // [12:4] DTag
input [31:13] t_di
;
input t_val_in
;
input t_be
;
input t_be_vb
;
input t_be_cb
;
input power_down_w
;
input dc_iiddtn
;
input wle_w
;
input [4:0] t_acc_in
;
input [7:0] t_cntx_in
;
input t_index3
;
input t_index2
;
input t_index1
;
input t_flush
;
input t_flush_user
;
input t_flush_user_cntx
;
input [4:0] t_at
;
input t_scan_mode
;
input t_tg_strobe
;
input t_clk
;
output [31:13] t_do
;
output t_val_out
;
output [4:0] t_acc_out
;
output [7:0] t_cntx_out
;
output t_hit
;
wire t_acc_hit
;
wire t_page_hit
;
wire t_segment_hit
;
wire t_region_hit
;
wire t_context_hit
;
wire t_user_hit
;
wire [8:0] ain_w ;
wire [31:13] di_w
;
wire [7:0] cntx_in_w
;
wire [4:0] acc_in_w
;
wire [4:0] at_w
;
wire val_in_w
, wle_w, be_w
, be_vb_w
, be_cb_w
;
// Register all of the inputs
// Address and VA-tag field span bits 31:4, regardless of size of
// cache (cache size is modelled as variable, for cache mode).
// Mflipflop_noop_9 a_reg(ain_w, t_ain, t_clk) ;
Mflipflop_noop_19 d_reg(di_w, t_di, t_clk) ;
Mflipflop_noop val_in_reg(val_in_w, t_val_in, t_clk) ;
Mflipflop_noop_8 cntx_in_reg(cntx_in_w, t_cntx_in, t_clk) ;
Mflipflop_noop be_reg(be_w, t_be, t_clk) ;
Mflipflop_noop be_vb_reg(be_vb_w, t_be_vb, t_clk) ;
Mflipflop_noop be_cb_reg(be_cb_w, t_be_cb, t_clk) ;
Mflipflop_noop_5 acc_reg(acc_in_w, t_acc_in, t_clk) ;
wire we_w
= ~power_down_w & wle_w & be_w ;
wire we_vb_w
= ~power_down_w & wle_w & be_vb_w ;
wire we_cb_w
= ~power_down_w & wle_w & be_cb_w ;
// synopsys translate_off
wire known_ain_w
= (^ain_w !== 1'bx) ;
wire illegal_control
=
((power_down_w^wle_w^be_w^be_vb_w^be_cb_w^t_scan_mode)
=== 1'bx)
| (power_down_w & (wle_w | be_w | be_vb_w | be_cb_w))
;
wire partial_pd_be
= (~power_down_w & ~wle_w & ~be_w) | power_down_w;
wire partial_pd_be_vb
= (~power_down_w & ~wle_w & ~be_vb_w) | power_down_w;
wire partial_pd_be_cb
= (~power_down_w & ~wle_w & ~be_cb_w) | power_down_w;
// synopsys translate_on
// Do the TAG, PROTECTION and FLUSH checks
////////////////////////////////////////////////////////////////////////
wire [31:13] tag_cmp
= (di_w^t_do) ;
// Decodes of access type (AT) of W-cycle access
parameter region_mask = 'hff000000>>13 ;
parameter segment_mask = 'h00fc0000>>13 ;
parameter page_mask = 'h0003f000>>13 ;
// Decodes of access permissions field (ACC) of addressed Tag.
assign t_acc_hit = (~(t_at[0] & t_acc_out[0] & t_flush)
& ~(t_at[1] & t_acc_out[1] & t_flush)
& ~(t_at[2] & t_acc_out[2] & t_flush)
& ~(t_at[3] & t_acc_out[3] & t_flush)
& ~(t_at[4] & t_acc_out[4] & t_flush));
assign t_region_hit = (t_index1 | ((tag_cmp & region_mask) == 0) );
assign t_segment_hit = (t_index2 | ((tag_cmp & segment_mask) == 0) );
assign t_page_hit = (t_index3 | ((tag_cmp & page_mask) == 0) );
// Context/user flush is slightly complicated ..
wire cntx_match_w
= (t_cntx_out==cntx_in_w) ;
// Note: t_acc_out[3] Indicates supervisor access
assign t_context_hit = ~(t_acc_out[3] | t_flush_user) ?
cntx_match_w :
~(t_acc_out[3] & t_flush_user_cntx) ;
assign t_hit = t_page_hit & t_segment_hit & t_region_hit &
t_acc_hit & t_context_hit & t_val_out;
// Do the read
wire read_ram_w
=
// synopsys translate_off
known_ain_w & ~illegal_control & ~partial_pd_be &
// synopsys translate_on
(we_w == 1'b0) ;
wire read_vb_w
=
// synopsys translate_off
known_ain_w & ~illegal_control & ~partial_pd_be_vb &
// synopsys translate_on
(we_vb_w == 1'b0) ;
wire read_cb_w
=
// synopsys translate_off
known_ain_w & ~illegal_control & ~partial_pd_be_cb &
// synopsys translate_on
(we_cb_w == 1'b0) ;
wire [31:13] t_do_int
;
wire [7:0] t_cntx_out_int
;
wire [4:0] t_acc_out_int
;
wire t_val_out_int
;
wire [31:13] di_w_int
=
// synopsys translate_off
illegal_control ? 19'bx :
// synopsys translate_on
di_w;
wire dtram_clk
= t_clk & t_tg_strobe;
wire we_w_int
= (~dtram_clk & we_w);
wire we_vb_w_int
= (~dtram_clk & we_vb_w);
assign t_do = read_ram_w ? t_do_int : 'bx ;
assign t_val_out = read_vb_w ? t_val_out_int : 'bx ;
assign t_cntx_out = read_cb_w ? t_cntx_out_int : 'bx ;
assign t_acc_out = read_cb_w ? t_acc_out_int : 'bx ;
// synopsys translate_off
// Error checks
always @(posedge t_clk) if (~t_scan_mode) begin
if ((^di_w === 1'bx) && (known_ain_w === 1'b1) && (we_w === 1'b1))
Mclocks.print_error( "writing unknown into DTag VA field") ;
if ((^val_in_w === 1'bx) && (known_ain_w === 1'b1) && (we_vb_w === 1'b1))
Mclocks.print_error( "writing unknown into DTag V-bit field") ;
if ((^we_w === 1'bx) && (known_ain_w === 1'b1))
Mclocks.print_error( "unknown DTag we_w") ;
if ((^we_vb_w === 1'bx) && (known_ain_w === 1'b1))
Mclocks.print_error( "unknown DTag we_vb_w") ;
if ((^we_cb_w === 1'bx) && (known_ain_w === 1'b1))
Mclocks.print_error( "unknown DTag we_cb_w") ;
if (illegal_control & ~`SS_SCOPE.reset)
Mclocks.print_error("Illegal DTag control") ;
if ((known_ain_w !== 1'b1) && (we_w|we_vb_w|we_cb_w))
Mclocks.print_error( "unknown DTag address during DTag write") ;
end
// synopsys translate_on
wire logic_one
= 1'b1;
// Turn off dtram during power down and IDDQ test
// correct for release 1.0
wire dc_iiddtn_
= ~dc_iiddtn;
// wire shutoff_dtram = power_down_w | dc_iiddtn ;
wire shutoff_dtram
= ~(power_down_w | dc_iiddtn_) ;
/*
RR512X33 dtram(
.ADR0 (ain_w[0]),
.ADR1 (ain_w[1]),
.ADR2 (ain_w[2]),
.ADR3 (ain_w[3]),
.ADR4 (ain_w[4]),
.ADR5 (ain_w[5]),
.ADR6 (ain_w[6]),
.ADR7 (ain_w[7]),
.ADR8 (ain_w[8]),
.DO32 (t_do_int[31]),
.DO31 (t_do_int[30]),
.DO30 (t_do_int[29]),
.DO29 (t_do_int[28]),
.DO28 (t_do_int[27]),
.DO27 (t_do_int[26]),
.DO26 (t_do_int[25]),
.DO25 (t_do_int[24]),
.DO24 (t_do_int[23]),
.DO23 (t_do_int[22]),
.DO22 (t_do_int[21]),
.DO21 (t_do_int[20]),
.DO20 (t_do_int[19]),
.DO19 (t_do_int[18]),
.DO18 (t_do_int[17]),
.DO17 (t_do_int[16]),
.DO16 (t_do_int[15]),
.DO15 (t_do_int[14]),
.DO14 (t_do_int[13]),
.DO13 (t_val_out_int),
.DO12 (t_cntx_out_int[7]),
.DO11 (t_cntx_out_int[6]),
.DO10 (t_cntx_out_int[5]),
.DO9 (t_cntx_out_int[4]),
.DO8 (t_cntx_out_int[3]),
.DO7 (t_cntx_out_int[2]),
.DO6 (t_cntx_out_int[1]),
.DO5 (t_cntx_out_int[0]),
.DO4 (t_acc_out_int[4]),
.DO3 (t_acc_out_int[3]),
.DO2 (t_acc_out_int[2]),
.DO1 (t_acc_out_int[1]),
.DO0 (t_acc_out_int[0]),
.DI32 (di_w_int[31]),
.DI31 (di_w_int[30]),
.DI30 (di_w_int[29]),
.DI29 (di_w_int[28]),
.DI28 (di_w_int[27]),
.DI27 (di_w_int[26]),
.DI26 (di_w_int[25]),
.DI25 (di_w_int[24]),
.DI24 (di_w_int[23]),
.DI23 (di_w_int[22]),
.DI22 (di_w_int[21]),
.DI21 (di_w_int[20]),
.DI20 (di_w_int[19]),
.DI19 (di_w_int[18]),
.DI18 (di_w_int[17]),
.DI17 (di_w_int[16]),
.DI16 (di_w_int[15]),
.DI15 (di_w_int[14]),
.DI14 (di_w_int[13]),
.DI13 (val_in_w),
.DI12 (cntx_in_w[7]),
.DI11 (cntx_in_w[6]),
.DI10 (cntx_in_w[5]),
.DI9 (cntx_in_w[4]),
.DI8 (cntx_in_w[3]),
.DI7 (cntx_in_w[2]),
.DI6 (cntx_in_w[1]),
.DI5 (cntx_in_w[0]),
.DI4 (acc_in_w[4]),
.DI3 (acc_in_w[3]),
.DI2 (acc_in_w[2]),
.DI1 (acc_in_w[1]),
.DI0 (acc_in_w[0]),
// Added port CS
.CS (shutoff_dtram),
.WE0 (we_w_int),
.WE1 (we_w_int),
.WE2 (we_w_int),
.WE3 (we_w_int),
.WE4 (we_w_int),
.WE5 (we_w_int),
.WE6 (we_w_int),
.WE7 (we_w_int),
.WE8 (we_w_int),
.WE9 (we_w_int),
.WE10 (we_w_int),
.WE11 (we_w_int),
.WE12 (we_w_int),
.WE13 (we_vb_w_int),
.WE14 (we_w_int),
.WE15 (we_w_int),
.WE16 (we_w_int),
.WE17 (we_w_int),
.WE18 (we_w_int),
.WE19 (we_w_int),
.WE20 (we_w_int),
.WE21 (we_w_int),
.WE22 (we_w_int),
.WE23 (we_w_int),
.WE24 (we_w_int),
.WE25 (we_w_int),
.WE26 (we_w_int),
.WE27 (we_w_int),
.WE28 (we_w_int),
.WE29 (we_w_int),
.WE30 (we_w_int),
.WE31 (we_w_int),
.WE32 (we_w_int),
.OE0 (logic_one),
.OE1 (logic_one),
.OE2 (logic_one),
.OE3 (logic_one),
.OE4 (logic_one),
.OE5 (logic_one),
.OE6 (logic_one),
.OE7 (logic_one),
.OE8 (logic_one),
.OE9 (logic_one),
.OE10 (logic_one),
.OE11 (logic_one),
.OE12 (logic_one),
.OE13 (logic_one),
.OE14 (logic_one),
.OE15 (logic_one),
.OE16 (logic_one),
.OE17 (logic_one),
.OE18 (logic_one),
.OE19 (logic_one),
.OE20 (logic_one),
.OE21 (logic_one),
.OE22 (logic_one),
.OE23 (logic_one),
.OE24 (logic_one),
.OE25 (logic_one),
.OE26 (logic_one),
.OE27 (logic_one),
.OE28 (logic_one),
.OE29 (logic_one),
.OE30 (logic_one),
.OE31 (logic_one),
.OE32 (logic_one)
);
*/
dtag_ram dtram
(
.ain({1'b0,ain_w}),
.din({di_w_int[31:13],val_in_w,cntx_in_w[7:0],acc_in_w[4:0]}),
.dout({t_do_int[31:13],t_val_out_int,t_cntx_out_int[7:0],t_acc_out_int[4:0]}),
.bw({{19{we_w_int}},we_vb_w_int,{13{we_w_int}}})
);
endmodule
//////////////////////////////////////////////////////////////////
This page: |
Created: | Thu Aug 19 12:00:17 1999 |
| From: |
../../../sparc_v8/ssparc/caches/mc_d_tag_cache/rtl/mc_dtag.v
|