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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)fifo4_next_4.v
***
***  Description:
***    Implements a 4 deep, 4 bit wide fifo, with the second read entry
***    viewable.  This holds the pci command, translated from afx address
***    space mapping.
*** 
****************************************************************************
****************************************************************************/


module fifo4_next_4(	
		reset,			//fifo reset
		clock,			//fifo clock
		data_in,		//data in (variable width)
		read,			//read fifo
		write,			//write fifo

		full_count,		//full count
 		data_out,		// fifo data out
		next_data_out		// fifo data out (rd_ptr +1)
		);
		

// Fifo is 4 entries deep, variable width default is 2 bit

// deviates slightly from the standard fifo in that the full count decrement
// from reads is delayed.  This is to take into consideration the asynch
// nature of reading the entries.  We need to be able to stream reads while
// the "ack" on reads is delayed for full handling.  The decrement signal
// will not be stable until 1/2 way through this clock.

	parameter WIDTH = 3;

input	reset;
input 	clock;
input	[WIDTH:0] data_in;
input   read;
input	write;

output [2:0] full_count;
output [WIDTH:0] data_out;
output [WIDTH:0] next_data_out;


reg [WIDTH:0] reg0,reg1,reg2,reg3;
reg [1:0] wr_ptr, rd_ptr, rd_ptr_plus1;
reg [2:0] full_count;

wire [WIDTH:0] data_out = mux4to1(rd_ptr, reg0, reg1, reg2, reg3);
wire [WIDTH:0] next_data_out = mux4to1(rd_ptr_plus1, reg0, reg1, reg2, reg3);

// load fifos and increment of read and write pointers

wire [1:0] rd_ptr_inc = rd_ptr + 2'b01;
wire [1:0] rd_ptr_plus_inc = read ? (rd_ptr_inc + 2'b01) : rd_ptr_inc;

always @(posedge clock)
  rd_ptr_plus1 <= #1 rd_ptr_plus_inc;

always @(posedge clock)
begin
  if (reset)
    begin
    reg0 <= 0;
    reg1 <= 0;
    reg2 <= 0;
    reg3 <= 0;
    end
  else if (write & wr_ptr == 2'b00)
    reg0 <= #1 data_in;
  else if (write & wr_ptr == 2'b01)
    reg1 <= #1 data_in;
  else if (write & wr_ptr == 2'b10)
    reg2 <= #1 data_in;
  else if (write & wr_ptr == 2'b11)
    reg3 <= #1 data_in;
end

always @(posedge clock)
begin

if (reset)
  begin
  rd_ptr <= 2'b00;
  end

else if (read)
    rd_ptr <= #1 (rd_ptr + 2'b01);
  
end

always @(posedge clock)
begin

if (reset)
  begin
  wr_ptr <= 2'b00;
  end

else if (write)
    wr_ptr <= #1 (wr_ptr + 2'b01);
  
end

// generate full_count;  0 at reset
// increment on write and no read
// decrement on read and no write
// holds on either no read, no write OR read and write
always @(posedge clock)
begin

if (reset )
  full_count <= 3'b000;

else if (write & ~read)
  full_count <= #1 (full_count + 3'b001);

else if (~write & read)
  full_count <= #1 (full_count - 3'b001);

end

// synopsys translate_off
always @(negedge clock)
  begin
  if (full_count > 3'b100)
    $display("ERROR, AFX command fifo full count > 4");
  end
// synopsys translate_on
function [WIDTH:0] mux4to1;
input [1:0] rd_ptr;
input [WIDTH:0] reg0;
input [WIDTH:0] reg1;
input [WIDTH:0] reg2;
input [WIDTH:0] reg3;

begin
case(rd_ptr)
  2'b00:	mux4to1 = reg0;
  2'b01:	mux4to1 = reg1;
  2'b10:	mux4to1 = reg2;
  2'b11:	mux4to1 = reg3;
endcase
end

endfunction


endmodule