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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)afx_slave_fifo.v
***
***  Description:
***    Implements the afx slave fifo's. This is just a logicless connection
***    of all the various afx fifo pieces.
*** 
****************************************************************************
****************************************************************************/


module afx_slave_fifo (
		clock,			
		reset,
		load_cmd_fifo, 		// load the command fifo 
		load_addr_fifo, 	// load address fifo from afx holding
		load_bm_fifo,		// load byte marks fifo from afx holding
		load_data_fifo,		// load data from afx holding 
		cmd_in,			// command fifo data into fifo
		addr_in,		// address in from afx holding
		bm_in,			// byte marks in from afx 
		afx_write_data,		// data in from afx holding
		read_cmd_fifo,		// read the command fifo to pci
		read_addr_fifo,		// read the address to pci
		read_bm_fifo,		// read the byte marks to pci
		read_data_fifo,		// read data to pci

		cmd_out,		// command out to pci
		next_cmd_out,		// command + 1 out to control logic
		addr_out,		// address out to pci
		next_addr_out,		// address + 1 out to control logic
		bm_out,			// byte marks out to pci & control
		data_out,		// data out to pci
		cmd_fifo_full_count, 	// command fifo full status to control
		data_fifo_full_count, 	// data fifo full status to control

		// add to support pci config operations
		pci_config_access_busy,
		config_add,
		config_data_in,

		pci_config_wdata,	// configuration write data lo word
		pci_config_wadd,	// configuration write address
		pci_config_radd		// configuration read address
		);

input		clock;
input 		reset;
input		load_cmd_fifo;
input		load_addr_fifo;
input		load_bm_fifo;
input		load_data_fifo;
input [3:0]	cmd_in;
input [28:0]	addr_in;
input [3:0]	bm_in;
input [63:0]	afx_write_data;
input		read_cmd_fifo;
input		read_addr_fifo;
input		read_bm_fifo;
input		read_data_fifo;

output [3:0]	cmd_out;
output [3:0]	next_cmd_out;

output [28:0]	addr_out;
output [28:0]	next_addr_out;

output [3:0]	bm_out;
output [63:0]	data_out;
output [2:0]	cmd_fifo_full_count;
output [2:0]	data_fifo_full_count;

output	[31:0]	pci_config_wdata;
output	[4:0]	pci_config_wadd;
output	[4:0]	pci_config_radd;

input		pci_config_access_busy;
input	[7:3]	config_add;
input	[31:0]  config_data_in;

wire	[31:0]	pci_config_wdata;
wire	[4:0]	pci_config_wadd;
wire	[4:0]	pci_config_tadd;
wire	[4:0]	pci_config_radd;

wire [3:0]	cmd_out;
wire [3:0]	next_cmd_out;

wire [28:0]	addr_out;
wire [28:0]	next_addr_out;

wire [3:0]	bm_out;
wire [63:0]	data_out;
wire [2:0]	cmd_fifo_full_count;
wire [2:0]	addr_fifo_full_count;
wire [2:0]	data_fifo_full_count;
wire [2:0]	bm_fifo_full_count;



// command fifo is 4 bits wide
fifo4_next_4  cmd_fifo(
		.reset			(reset),
		.clock			(clock),
		.data_in		(cmd_in),
		.read			(read_cmd_fifo),
		.write			(load_cmd_fifo),

		.full_count		(cmd_fifo_full_count),
		.data_out		(cmd_out),
		.next_data_out		(next_cmd_out) 
		);

// address fifo is 29 bits wide
fifo4_next_29  address_fifo(
		.reset			(reset),
		.clock			(clock),
		.data_in		(addr_in),
		.read			(read_addr_fifo),
		.write			(load_addr_fifo),

		.full_count		(addr_fifo_full_count),
		.data_out		(addr_out),
		.next_data_out		(next_addr_out) 
		);


// data fifo is 64 bits wide doesn't need view of next entries
fifo4_64  data_fifo(
		.reset			(reset),
		.clock			(clock),
		.data_in		(afx_write_data),
		.read			(read_data_fifo),
		.write			(load_data_fifo),

		.full_count		(data_fifo_full_count),
		.data_out		(data_out)
		);

// byte mark fifo is 8 bits wide doesn't need view of next entries
fifo4_4  bm_fifo(
		.reset			(reset),
		.clock			(clock),
		.data_in		(bm_in),
		.read			(read_bm_fifo),
		.write			(load_bm_fifo),

		.full_count		(bm_fifo_full_count),
		.data_out		(bm_out)
		);

assign pci_config_wdata = pci_config_access_busy ? config_data_in : 
				data_out[31:0];

assign pci_config_wadd = pci_config_access_busy ? config_add[7:3] : addr_out[4:0];
assign pci_config_radd = pci_config_access_busy ? config_add[7:3] : addr_out[4:0];
assign pci_config_tadd = pci_config_access_busy ? config_add[7:3] : addr_out[4:0];

endmodule