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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)icceval.v
***
****************************************************************************
****************************************************************************/
//------------------------------------------------------------------------------


module Micceval(bicc_taken,
	d_cond, ccm, alu_cc_next, load_cc,
	eopc_hidiv3, det_divovf, ccN_noninv, ccZ_noninv
	);

/*
 * For SUNERGY Puma: d_cond used to be condm, but was changed since
 * we need to decide if a branch is taken in the D cycle of the branch.
 * condm is in the E-cycle.
 */

output	bicc_taken;		// Integer CC's + COND evaluate TRUE in D
input [3:0] d_cond;		// master latched COND field of BICC in D
input [3:0] ccm;		// master latched condition codes
input [3:0] alu_cc_next;	// CC's direct from ALU
input load_cc;			// control to select ALU's CC.
input eopc_hidiv3;		// hidiv 3 in E
input det_divovf;		// ovf detected in IDIV
input ccN_noninv;		// non-inverted ccN (alu_cc_next[3]) from Mexec
input ccZ_noninv;		// non-inverted ccZ (alu_cc_next[2]) from Mexec

	wire [1:0] alu_cc_lo;

	assign alu_cc_lo[1] =
		  alu_cc_next[1] & ~eopc_hidiv3
		| eopc_hidiv3 & det_divovf;

	assign alu_cc_lo[0] =
		  alu_cc_next[0] & ~eopc_hidiv3;

// note that the control logic receives alu_cc_next[3:2] inverted.
//  we must reinvert here. ======> this is old note
// 9-15-96 : to speed up path, bring in non-inverted signals from Mexec.
// wire alu_cc_next_act3 = ~alu_cc_next[3];
// wire alu_cc_next_act2 = ~alu_cc_next[2]; 

	wire Nm =
		// synopsys translate_off
		(load_cc===1'bx) ? 'bx :
		// synopsys translate_on
		load_cc ? ccN_noninv : ccm[3];
	wire Zm =
		// synopsys translate_off
		(load_cc===1'bx) ? 'bx :
		// synopsys translate_on
		load_cc ? ccZ_noninv : ccm[2];
	wire Vm =
		// synopsys translate_off
		(load_cc===1'bx) ? 'bx :
		// synopsys translate_on
		load_cc ? alu_cc_lo[1] : ccm[1];
	wire Cm =
		// synopsys translate_off
		(load_cc===1'bx) ? 'bx :
		// synopsys translate_on
		load_cc ? alu_cc_lo[0] : ccm[0];

	reg bicc_taken;

	always @ (d_cond or Nm or Zm or Vm or Cm) begin
		
		case (d_cond[2:0])	/* synopsys parallel_case */

			3'b000:	// BN
				bicc_taken = 0;

			3'b001:	// BE
				bicc_taken = Zm;

			3'b010:	// BLE
				bicc_taken = Zm | (Nm ^ Vm);

			3'b011: // BL
				bicc_taken =  Nm ^ Vm;

			3'b100:	// BLEU
				bicc_taken = Cm | Zm;

			3'b101:	// BCS, GEU
				bicc_taken =  Cm;

			3'b110:	// BNEG
				bicc_taken =  Nm;

			3'b111:	// BVS
				bicc_taken = Vm;

/* synopsys translate_off */
			default:
				bicc_taken = 'bx;
/* synopsys translate_on */
		endcase

		if(d_cond[3])
			bicc_taken = ~bicc_taken;
	end

endmodule