wr_mulscc,
        use_hi_alu,
        use_hi_rs1_default,
        use_hi_rs2,
        use_hi_rs2_default,
	not_rs2_rs1_default,
        use_hi_y,
	shift_left,
	arith_shift,
	force_neg,
	force_pos
	);

	wire use_low_rs1 = dopc_hidiv3_op;
	wire sel_sll1_divalu = eopc_hidiv1;

Mpc_control pc_control(
        TRAP,
        ss_clock,
        d_hop,
        d_nop,
        d_trap,
	e_hop3,
        fcc_ilock,
        hold,
        interlock,
        nERROR,
        nreset,
        reset,
	ss_scan_mode,
        valid_decode,
        e_call,
        e_jmprett,
        hld_dpc,
	hld_dum_dpc,
        sadr_jmprett,
        sadr_tbr,
        sadr_zero
        );

// assign aas1_call = in_dec_hi_30;

Mspecial_reg_control special_reg_control(
	TRAP,
        ss_clock,
	d_opcode,
	dopc_hidiv0_op,
	dopc_himulcc2,
	dopc_hidivcc3,
        d_trap,
        e_hop3,
        et,
	fold_annul6,
	help_ctr[0],
	help_ctr[1],
        hold,
	hnop_into_ex,
	htrap_into_ex,
	nERROR,
	ns,
        psm,
        reset,
	ss_scan_mode,
        sm,
	sv_rest_recirc,
        trap_cyc1,
        valid_decode,
	valid_decode_nilock,
        w_hop3,
        alternate_e,
        clret_sets,
        cwp_dec,
        cwp_hold,
        cwp_inc,
	cwp_recirc,
	wcwpm1,
	cwpp1,
	cwpm1,
	wcwp,
	cwp,
        e_jmpcallm,
        e_rdpsrm,
        e_rdtbrm,
        e_rdwimm,
        e_rdym,
	sel_pcspec_l,
        ecwp_next,
        hld_pilefec,
        hld_tba,
        hld_tt,
	n_hld_tt_scan,
        hld_wim,
        hold_cc,
        hold_ets,
        hold_ps,
        load_cc,
	nalternate_e,
        normal_asi0,
        rdtpcm,
        restore_cc,
        s_into_ps,
	setcc,
        setet_ps2s,
        w_wrpsr,
        write_cc,
        write_etps,
	e_rdpsr_op,
	e_rdtbr_op,
	e_rdwim_op,
	e_rdy_op,
	e_rdy_op_forilock,
	use_ps
);


Mdcache_control dcache_control(
        alu_out_lsb5[1:0],
	d_asi,
	d_opcode,
	fold_annul4,
	nalternate_e,
	reset,
	valid_decode,
	hold,
	ss_clock,
	TRAP,
        byte_mark0_e,
        byte_mark1_e,
        byte_mark2_e,
        byte_mark3_e,
	ld_op_e,
	ld_op_e_mmu,
	ld_op_d,
	sgnd_ld_e,
	st_op_e,
	st_op_e_mmu,
	st_op_d,
	fpu_mem_e,
	iu_iflush_e,
	size_e
);

/*
 * removed - see iu.iuchip.Mhold_control and see
 * Mir_control for hld_dirreg
Mhold_control hold_control(
	FHOLD,
        ss_clock,
	dwait_w,
	dt_hit_w,
	dc_shold,
	enbl_dtag_match_w,
	enbl_itag_match_f,
        gen_help,
	iwait_f,
	it_hit_f,
        interlock,
//        jmp_ilock, 
        reset,
        valid_decode_nil_imh,
        w_hop3, 
	hld_dirreg,
	hld_dirreg_trunc,
        hold, 
	iu_pipe_hold,
	hold_noic,
	hold_ic,
	extend_tag_miss
	);
 */


Mfp_control fp_control(
        e_hop3, 
	w_hop3,
        select_FP_DOUT,
	sel_ldstb_1,
	select_IU_DOUT
	);


Mtrap_detection trap_detection(
        ANNUL,
        TRAP,
        ccm[1],   
        alu_out_lsb5,
        bicc_taken,
	alu_cc_next[2],
        ss_clock,
        cwpm_,
        d_hop3,
        d_imm,
	ehop3_idivbasic,
        mm_iacc_exc_d,
	mm_iacc_err_tlb_d,
	mm_iacc_wp_exc_d,
	parity_error_d,
	mm_iacc_mmu_miss_d,
        d_nop,
        d_trap,
        e_hop3,
        ef,
        et,
	fold_annul7,
        fp_exc,
        hold,
	mispredicted,
//      mm_dacc_exc_w,
//	mm_dacc_err_w,
//	mm_dacc_mmu_miss_w,
        int_req_lev,
        interlock,
        pil,
        reset,
        s,
	trapcode,
        trap_cyc1,
        valid_decode,
	w_wrpsr,
        wimm,
        ERROR_nop,
        ER_SDOUT,
	error_mode,
	iu_event,
        nERROR,
        trapd_cpd,
        trapd_fpd,
        trapd_iae,
        trapd_iaer,
	trapd_immum,
	trapd_iwp,
        trapd_ilgl,
        trape_algn,
        trape_ilgl,
        trape_priv,
        trape_ticc,
        trape_wo,
        trape_wu,
//      trapw_dae,
//	trapw_daer,
//	trapw_dmmum,
        trapw_fpe,
        trapw_int,
        trapw_tag,
	trape_divz
	);

//	wire iu_trapd_iaer = trapd_iaer;

Mtrap_control trap_control (
        FEXC,
	nERROR,
        ss_clock,
	fold_annul3,
        hold,
        pint_req_lev,
        reset,
        result_lo,
        trapd_cpd,
        trapd_fpd,
        trapd_iae,
        trapd_iaer,
	trapd_immum,
	trapd_iwp,
        trapd_ilgl,
        trape_algn,
        trape_ilgl,
        trape_priv,
        trape_ticc,
        trape_wo,
        trape_wu,
	mm_dacc_exc_w,
	mm_dacc_err_w,
	mm_dacc_mmu_miss_w,
	mm_dacc_wp_w,
//      trapw_dae,
//	trapw_daer,
//	trapw_dmmum,
        trapw_fpe,
        trapw_int,
        trapw_tag,
	trape_divz,
        FXACK,
        IU_in_trap,
	IU_in_trap4fpu,
	IU_in_trap4dc,
        TRAP,
        d_trap,
        fp_exc,
        trap_cyc1,
        trap_cyc2,
        trapcode,
        w_trap,
	wo_trap_w,
	wu_trap_w
	);

//---------------------------------------------------------------
// Control logic for GPC and FPC address generation, Queue state
// machine, and assorted other stuff.
	wire [3:0] dbr_cond;
	wire nfold_taken;

        Mpc_cntl pc_cntl (
        .sel_lta_fpc    (sel_lta_fpc),
        .sel_idpc_fpc   (sel_idpc_fpc),
        .sel_post_reset (sel_post_reset),
        .sel_p_fpc      (sel_p_fpc),
        .sel_alt_tag    (sel_alt_tag),
	.sel_i1pfpc_fpc	(sel_i1pfpc_fpc),
        .sel_i2dpc_fpc  (sel_i2dpc_fpc),
        .fetch_ic_even  (fetch_ic_even),
        .fetch_ic_odd   (fetch_ic_odd),
        .fetch_TOQ      (fetch_TOQ),
        .fetch_alt      (fetch_alt),
        .fetch_SIQ      (fetch_SIQ),
	.ncant_unload	(ncant_unload),
        .hold_alt       (hold_alt),

        .fold_annul     (fold_annul),
        .fold_annul2    (fold_annul2),
        .fold_annul3    (fold_annul3),
        .fold_annul4    (fold_annul4),
        .fold_annul5    (fold_annul5),
        .fold_annul6    (fold_annul6),
        .fold_annul7    (fold_annul7),

	.nfold_annul	(nfold_annul),
	.mispredicted	(mispredicted),
        .untaken_empty_ilock (untaken_empty_ilock),
	.sv_rest_fold_ilock	(sv_rest_fold_ilock),
	.sv_rest_recirc	(sv_rest_recirc),
        .sel_shift1     (sel_shift1),
        .sel_shift2     (sel_shift2),
        .sel_shift3     (sel_shift3),
        .sel_fold1      (sel_fold1),
        .sel_fold2      (sel_fold2),
        .sel_even1      (sel_even1),
        .sel_odd1       (sel_odd1),
        .hold_q1        (hold_q1),
        .sel_even2      (sel_even2),
        .sel_odd2       (sel_odd2),
        .hold_q2        (hold_q2),
        .sel_even3      (sel_even3),
        .sel_odd3       (sel_odd3),
        .hold_q3        (hold_q3),
        .hold_q4        (hold_q4),
        .sel_last_gen   (sel_last_gen),
        .recirc2_default      (recirc2_default),
        .sel_inc_ll_gen (sel_inc_ll_gen),
        .sel_inc_dpc    (sel_inc_dpc),
        .sel_inc_alttag (sel_inc_alttag),
        .sel_gpc        (sel_gpc),
        .sel_recirc     (sel_recirc),
        .sel_recirc_inc (sel_recirc_inc),
	.sel_lgen_iva	(sel_lgen_iva),
        .sel_gpc_ic      (sel_gpc_ic),
        .sel_recirc_ic   (sel_recirc_ic),
        .sel_recirc_inc_ic	(sel_recirc_inc_ic),
	.sadr_zero_ic	(sadr_zero_ic),
	.force_ifill	(force_ifill),
	.flush_ic_e	(flush_ic_e),
	.force_dva	(force_dva),
        .fwd_wpc        (fwd_wpc),
        .use_tpc        (use_tpc),
        .fwd_tpcm4      (fwd_tpcm4),
	.lta_hold	(lta_hold),
	.dbr_cond	(dbr_cond),
	.hld_car_mar	(hld_car_mar),
	.hld_lgens	(hld_lgens),
	.hld_backup	(hld_backup),
	.take_icdata	(take_icdata),
	.sel_old_aa	(sel_old_aa),
	.hld_dir2	(hld_dir2),
	.sel_lgen_ica	(sel_lgen_ica),
	.stop_fetch	(stop_fetch),
	.did_fetch	(did_fetch),
	.nANNUL		(nANNUL),
	.s		(s),
        .fcc_taken      (fcc_taken),
        .bicc_taken     (bicc_taken),
        .d_hop3         (d_hop3),
        .e_opcode_hi    (e_opcode[10:2]),
        .w_hop3         (w_hop3),
        .iu_fetch_f     (iu_fetch_f),
        .gen_help       (gen_help),
	.gen_help_op	(gen_help_op),
	.nfold_taken	(nfold_taken),
        .IU_in_trap     (IU_in_trap),
	.TRAP		(TRAP),
	.ER_SDOUT	(ER_SDOUT),
	.trap_cyc1	(trap_cyc1),
        .trap_cyc2      (trap_cyc2),
        .fpc_low        (fpc_low),
	.nlta_low	(nlta_low),
	.ndpc_low	(ndpc_low),
	.nalttag_low	(nalttag_low),
        .iacc_exc_mmumiss_d        (iacc_exc_mmumiss_d),
	.d_nop		(d_nop),
	.d_trap		(d_trap),
	.fcc_ilock	(fcc_ilock),
        .sadr_jmprett   (sadr_jmprett),
        .sadr_tbr       (sadr_tbr),
	.sadr_zero	(sadr_zero),
        .toq_entry_bits (toq_entry_bits),
	.nq1_entry_hi	(nq1_entry_hi),
	.iexc_for_br	(iexc_for_br),
	.niexc1_hi	(niexc1_hi),
        .ilock          (interlock),
        .valid_decode   (valid_decode),
	.valid_decode_nilock	(valid_decode_nilock),
	.hold_noic	(hold_noic),
	.hold_ic	(hold_ic),
	.iu_asi_e_4	(iu_asi_e[4]),
	.ic_force_ifill_g	(ic_force_ifill_g),
	.mm_istat_avail	(mm_istat_avail),
	.i_dva_req	(i_dva_req),
	.iwait_f	(iwait_f),
	.dwait_w_for_flush	(dwait_w_for_flush),
//	.extend_tag_miss	(extend_tag_miss),
	.enbl_br_fold	(enbl_br_fold),
	.start_itag_inv	(start_itag_inv),
	.q3_iae		(q3_iae),
	.q3_ptc		(q3_ptc),
	.q2_iae		(q2_iae),
	.q2_ptc		(q2_ptc),
	.q1_iae		(q1_iae),
	.q1_ptc		(q1_ptc),
	.hnop_into_ex	(hnop_into_ex),
	.wo_trap_w	(wo_trap_w),
	.wu_trap_w	(wu_trap_w),
        .ss_clock       (ss_clock),
        .hold           (hold),
        .reset          (reset),
	.del_resetm	(del_resetm)
        );

//------------------------------------------------------------------------------// INTERFACE MODULE



        Minterface interface ( ss_reset, nnreset, nreset, reset,
                del_resetm,
		iexc_for_int_hi,
		mm_iacc_exc_d,
		mm_iacc_mmu_miss_d,
		mm_iacc_err_tlb_d, mm_iacc_wp_exc_d, parity_error_d,
		iacc_exc_mmumiss_d,
		this_s, sup_ex_trap,
                IRL, int_req_lev, pint_req_lev,
		hld_dirreg, hold,
                e_asim, alternate_e,
                iu_asi_e,
		use_ps, s, psm,
                ss_clock, ANNUL, d_nop, d_trap
                );

	wire iu_mm_iacc_wp_exc_d = mm_iacc_wp_exc_d;

/*
	wire iu_mm_dacc_exc_r = dacc_exc_err_mmumiss_r;
*/
//----------------------------------------------------------------
//	wire [3:0] ccm;
//	wire [3:0] alu_cc;
// setcc was load_cc - setcc isn't qualified by TRAP like load_cc

        Micceval icceval (bicc_taken,
                d_cond, ccm, alu_cc_next, setcc,
		eopc_hidiv3, det_divovf, ccN_noninv, ccZ_noninv
        );

	Micceval icceval_fold (nfold_taken,
		dbr_cond, ccm, alu_cc_next, setcc,
		eopc_hidiv3, det_divovf, ccN_noninv, ccZ_noninv
        );


//--------------------------------------------------------------------------
// Mir block moved from top level and merged into Mdecode

        Mir ir (
                .e_op           (e_op),
                .e_op3          (e_op3),
                .w_op           (w_op),
                .w_op3          (w_op3),
                .d_rs1          (d_rs1),
                .nbrs1_decm     (nbrs1_decm),
                .brs3_d         (brs3_d),
                .e_rd           (e_rd),
                .w_rdm          (w_rd),
                .w_rdp          (w_rdp),
                .nr_rdp         (nr_rdp),
                .in_dec         (in_dec),
                .d_imm_l        (d_imm_l),
                .e_asim         (e_asim),
                .iu_sfs_sup     (iu_sfs_sup),
                .iu_sfs_perr    (iu_sfs_perr),
                .iu_sfs_xerr    (iu_sfs_xerr),
                .iu_sfs_mmiss   (iu_sfs_mmiss),
                .iu_sfs_iae     (iu_sfs_iae),
                .iu_sfs_sbe     (iu_sfs_sbe),
                .iu_sfs_sto     (iu_sfs_sto),
                .iu_sfs_prtct   (iu_sfs_prtct),
                .iu_sfs_priv    (iu_sfs_priv),
                .iu_sfs_lvl     (iu_sfs_lvl),
                .inst_for_int   (inst_for_int),
                .ndec_inst_traps        (ndec_inst_traps),
                .hld_dirreg     (hld_dirreg),
                .ecwpm_         (ecwpm_),
                .ncwpm_l        (ncwpm_l),
                .hnop_into_ex   (hnop_into_ex),
                .htrap_into_ex  (htrap_into_ex),
                .clr_e_iexc_nop (clr_e_iexc_nop),
                .set_rd0m       (set_rd0m),
                .clear_rd0m     (clear_rd0m),
                .d_rd_hstd_sel  (d_rd_hstd_sel),
                .write_r15      (write_r15),
                .write_r18      (write_r18),
                .result_r0      (result_r0),
                .TRAP           (TRAP),
                .fold_annul     (fold_annul6),
		.ss_clock	(ss_clock),
                .hold           (hold)
                );



//------------------------------------------------------------------------------
// NOT REAL HARDWARE
// The code below is an automatic check of the FPU's E-cycle PC value
// and FP instruction against what the IU thinks it should be.
// synopsys translate_off
	wire d_fpins =
		valid_decode & d_hop3==`FPOP | d_hop3==`FPCMP
		;

	wire e_fpins;
	Mflipflop_1 fpins_reg_1( e_fpins, d_fpins, ss_clock, hold | ss_scan_mode) ;

/*
 * Removed from SUNERGY
	always @ (negedge ss_clock) begin
		if (e_fpins) begin
			if(Msystem.fpu.UC.addrE != Msystem.iu.iuchip.pc.epc<<2)

				$display("*** FPU WRONG XPC epc=%x addrE=%x",
				Msystem.iu.iuchip.pc.epc<<2, Msystem.fpu.UC.addrE);

			if(Msystem.fpu.UC.fpinsE_op3
					!= Msystem.iu.iuchip.ir.in_exa[24:19])

				$display("*** FPU WRONG OP3 iu: %x fpc: %x",
					Msystem.iu.iuchip.decode.ir.in_exa[24:19],
					Msystem.fpu.UC.fpinsE_op3);
		end
	end

 *
 * End of removal from SUNERGY
 */
// synopsys translate_on

endmodule


//------------------------------------------------------------------------------


// co-processor and FP condition code evaluation logic


module Mfcc_eval (taken, d_cond, scc);
output taken;		// result of evaluation
input [3:0] d_cond;	// condition selector
input [1:0] scc;	// encoded condition codes

	reg taken;

	// decode cc's

	wire E = scc==2'b0;
	wire L = scc==2'b01;
	wire G = scc==2'b10;
	wire U = scc==2'b11;

	always @ (d_cond or E or L or G or U) begin
		case (d_cond) /* synopsys parallel_case */

		4'b0000:	taken = 0;		// BN (never)
		4'b1000:	taken = 1;		// BA (always)

		4'b0001:	taken = L | G | U;	// BNE
		4'b1001:	taken = E;		// BE

		4'b0010:	taken = L | G;		// BLG
		4'b1010:	taken = U | E;		// BUE

		4'b0011:	taken = L | U;		// BUL
		4'b1011:	taken = G | E;		// BGE

		4'b0100:	taken = L;		// BL
		4'b1100:	taken = E | G | U;	// BUGE

		4'b0101:	taken = G | U;		// BUG
		4'b1101:	taken = L | E;		// BLE

		4'b0110:	taken = G;		// BG
		4'b1110:	taken = U | L | E;	// BULE

		4'b0111:	taken = U;		// BU
		4'b1111:	taken = G | L | E;	// BO

/* synopsys translate_off */
		default:	taken = 'bx;
/* synopsys translate_on */

		endcase
	end

endmodule



module reg_cmp5 (same, side1, side2);

/*
	This module is a five bit comparator module.
	Use in place of "==" for variable to variable
	compares of 5 bit.

	When the operands are equal, same = 1.

	When compile in synopsys, use no_flatten.
*/

output same;
input [4:0] side1;
input [4:0] side2;

	wire eq0 = side1[0] ~^ side2[0];
	wire eq1 = side1[1] ~^ side2[1];
	wire eq2 = side1[2] ~^ side2[2];
	wire eq3 = side1[3] ~^ side2[3];
	wire eq4 = side1[4] ~^ side2[4];

	wire same_3 = eq0 & eq1 & eq2;
	wire same_2 = eq3 & eq4;

	wire same = same_2 & same_3;

endmodule


module reg_cmp4 (same, side1, side2);

/*
	This module is a four bit comparator module.
	Use in place of "==" for variable to variable
	compares of 4 bit.

	When the operands are equal, same = 1.

	When compile in synopsys, use no_flatten.
*/

output same;
input [3:0] side1;
input [3:0] side2;

	wire eq0 = side1[0] ~^ side2[0];
	wire eq1 = side1[1] ~^ side2[1];
	wire eq2 = side1[2] ~^ side2[2];
	wire eq3 = side1[3] ~^ side2[3];

	wire same_3 = eq0 & eq1 & eq2;

	wire same = same_3 & eq3;

endmodule


module reg_cmp3 (same, side1, side2);

/*
	This module is a three bit comparator module.
	Use in place of "==" for variable to variable
	compares of 3 bit.

	When the operands are equal, same = 1.

	When compile in synopsys, use no_flatten.
*/

output same;
input [2:0] side1;
input [2:0] side2;

	wire eq0 = side1[0] ~^ side2[0];
	wire eq1 = side1[1] ~^ side2[1];
	wire eq2 = side1[2] ~^ side2[2];

	wire same = eq0 & eq1 & eq2;

endmodule


module reg_cmp2 (same, side1, side2);

/*
	This module is a two bit comparator module.
	Use in place of "==" for variable to variable
	compares of 2 bit.

	When the operands are equal, same = 1.

	When compile in synopsys, use no_flatten.
*/

output same;
input [1:0] side1;
input [1:0] side2;

	wire eq0 = side1[0] ~^ side2[0];
	wire eq1 = side1[1] ~^ side2[1];

	wire same = eq0 & eq1;

endmodule



module reg_cmp8 (same, side1, side2);

/*
	This module is a seven bit comparator module.
	Use in place of "==" for variable to variable
	compares of 8 bits.

	When the operands are equal, same = 1.

	When compile in synopsys, use no_flatten.
*/

output same;
input [7:0] side1;
input [7:0] side2;

	wire eq0 = side1[0] ~^ side2[0];
	wire eq1 = side1[1] ~^ side2[1];
	wire eq2 = side1[2] ~^ side2[2];
	wire eq3 = side1[3] ~^ side2[3];
	wire eq4 = side1[4] ~^ side2[4];
	wire eq5 = side1[5] ~^ side2[5];
	wire eq6 = side1[6] ~^ side2[6];
	wire eq7 = side1[7] ~^ side2[7];

	wire same_3 = eq0 & eq1 & eq2;
	wire same_2 = eq3 & eq4;
	wire same_1 = eq5 & eq6 & eq7;

	wire same = same_2 & same_3 & same_1;

endmodule

/************************************************************/

/************************************************************/


module Mtrapw_int (trapw_int, pil, irl_l, et, no_interrupts_l,
	hold, ss_clock);
output trapw_int;
input [3:0] pil;
input [3:0] irl_l;
input et;
input no_interrupts_l;
input hold;
input ss_clock;

/*
   The following new solution is based on the observation that the carry-out
   of (int_req_lev[3:0] + ~pil[3:0]) is int_req_lev > pil. This carry
   out (C3) is:
 
                C3 = G3 | G2 & P3 | G1 & P2 & P3 | G0 & P1 & P2 & P3
        
   where the P terms and G terms are the propagate and generate (OR and AND)
   for each bit pair.
        
   to handle the non-maskable case, an additional term: 
                
          (int_req_lev[3] & int_req_lev[2] & int_req_lev[1] & int_req_lev[0])
        
   is ored in. Implementation consists of 3 AND gates to compute the P terms
   (inverted) and 5 NOR gates to compute each product term followed by a
   wire-or of the 5 product terms.
*/

        /* carry propagate terms for int_req_lev + ~irl */
        wire p1_ = irl_l[1] & pil[1];
        wire p2_ = irl_l[2] & pil[2];
        wire p3_ = irl_l[3] & pil[3];
 
        wire irq =(
                  (~(p1_ | p2_ | p3_ | pil[0] | irl_l[0]))       // NOR5C_HW
                | (~(      p2_ | p3_ | pil[1] | irl_l[1]))       // NOR4C_HW
                | (~(            p3_ | pil[2] | irl_l[2]))       // NOR3C_HW
                | (~(                  pil[3] | irl_l[3]))       // NOR2C_HW
                | (~(irl_l[0] | irl_l[1] | irl_l[2] | irl_l[3]))    // NOR4C_HW
                ) 
                ;

//	wire trapw_int = et & no_interrupts_l & irq;

	wire trapw_int_val;
	Mflipflop_1 trapw_int_val_reg_1(trapw_int_val,irq,ss_clock,hold) ;

	wire p_et;
	Mflipflop_1 p_et_reg_1(p_et,et,ss_clock,hold) ;

	wire trapw_int = p_et & no_interrupts_l & trapw_int_val;
endmodule


module Mtrapcode (
	wfpe, dae, daer, dmmum, immum, iwp_det, dwp_det,
	iae, ilgl, divz, ilgl2, priv, fpd,
	iaer, cpd, wo, wu, algn, tag, ticc, int,
	hold, pint_req_lev, result, nERROR,
	trapcode, FXACK);

input wfpe;
input dae, daer, dmmum, immum, iwp_det, dwp_det;
input iae, ilgl, divz, ilgl2, priv, fpd;
input iaer, cpd, wo, wu, algn, tag, ticc, int;
input hold;
input [3:0] pint_req_lev;
input [6:0] result;
input nERROR;
output [7:0] trapcode;
output FXACK;


	reg [7:0] trapcode;

	always @ (wfpe or dae or daer or dmmum or immum or iwp_det or dwp_det
			or iae or ilgl or divz
			or ilgl2 or priv or fpd or iaer
			or cpd or wo or wu or algn or tag or ticc or result
			or int or pint_req_lev) begin

		// synopsys translate_off
		if ((daer^dmmum^dae^immum^iaer^iae^priv^ilgl^ilgl2
			^fpd^cpd^wo^wu^algn^wfpe^tag^divz^ticc^int)===1'bx)
			trapcode = 8'bx;
		else
		// synopsys translate_on

		if	(immum) trapcode = 60;
		else if (iaer) trapcode = 33;
		else if (iae) trapcode = 1;
		else if (priv) trapcode = 3;
		else if (ilgl | ilgl2) trapcode = 2;
		else if (fpd) trapcode = 4;
		else if (cpd) trapcode = 36;
		else if (iwp_det | dwp_det) trapcode = 11;
		else if (wo) trapcode = 5;
		else if (wu) trapcode = 6;
		else if (algn) trapcode = 7;
		else if (wfpe) trapcode = 8;
		else if	(daer) trapcode = 41;  // R cycle traps #1 priority
		else if (dmmum) trapcode = 44;
		else if (dae) trapcode = 9;
		else if (tag) trapcode = 10;
		else if (divz) trapcode = 42;
		else if (ticc)  trapcode = {1'b1, result[6:0]};
		else if (int) trapcode = {4'b0001, pint_req_lev};
		else trapcode = 0;
	end

// trap prioritization and encoding logic

//
//	wire pfpe = (~dae & ~daer & ~iaer & ~iae & ~priv & ~ilgl & ~ilgl2
//	  & ~fpd & ~cpd & ~wo & ~wu & ~algn & ~immum & ~dmmum & wfpe);

	wire pfpe = (~iaer & ~iae & ~priv & ~ilgl & ~ilgl2
	  & ~fpd & ~cpd & ~wo & ~wu & ~algn & ~immum & wfpe);

// This is the FP exception acknowledge signal.

	wire FXACK = pfpe & ~nERROR;

endmodule