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//  @(#)normcalslice.v	1.1  4/7/92
//

module NormCalSlice (NI, notsh, notNO);
input [15:0] NI; 
output [3:1] notsh;
output [1:0] notNO;

wire   [3:0] notNR ;  

   twosch     m1 (NI[7:0],  sh1a, sh2a, notNR[1:0]);
   twosch_top m2 (NI[15:8], sh1b, sh2b, notNR[3:2], NR1and0);
   onesch_sp  m3 (notNR[3:0],  notsh[3], notNO[1:0]);

   // anything set on top then take s1 , s2 from top 
   ME_NMUX2B    m4 (NR1and0, sh1a, sh1b, notsh[1]); 
   ME_NMUX2B    m6 (NR1and0, sh2a, sh2b, notsh[2]); 
                                                  
endmodule


module twosch (NI[7:0],sh1,sh2,notNO[1:0] );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
wire   [3:0] notNR ;

   onesch    m1 (NI[3:0], notsh1a, notNR[1:0]);
   onesch    m2 (NI[7:4], notsh1b, notNR[3:2]);
   notonesch m3 (notNR[3:0], sh2,  notNO[1:0]);
   // anything set on top then take s1 from top 
   ME_NMUX2B    m4 (notNO[1], notsh1b, notsh1a, sh1 ); 

endmodule


module twosch_top (NI[7:0],sh1,sh2,notNO[1:0], NO1and0 );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
output NO1and0 ;
wire   [3:0] notNR ;

   onesch    m1 (NI[3:0], notsh1a, notNR[1:0]);
   onesch    m2 (NI[7:4], notsh1b, notNR[3:2]);
   notonesch m3 (notNR[3:0], sh2,  notNO[1:0]);
   // anything set on top then take s1 from top 
   ME_NMUX2B_B  m4 (notNO[1], notsh1b, notsh1a, sh1 ); 
   ME_NAND4     m5 (notNR[0], notNR[1], notNR[2], notNR[3], NO1and0);
   // Special
endmodule


module onesch (NI[3:0], notsh1, notNR[1:0]);
  input [3:0] NI;
  output notsh1;
  output [1:0] notNR ;

  ME_INV_A i1 (NI[1],             notNI1);
  ME_NOR2 i2 (NI[2], notNI1,   notBornotC);
  ME_OR2  i3 (NI[3], notBornotC, notsh1);
//  ME_INV_A  i1 (NI[1],             notNI1);
//  ME_INV_A  i2 (NI[3],             notNI3);
//  ME_O2A1I i3 (notNI1, NI[2], notNI3, notsh1);
  ME_NOR2_B r4 (NI[0], NI[1], notNR[0] );
  ME_NOR2_B r5 (NI[2], NI[3], notNR[1] );
endmodule


module notonesch (notNI[3:0], sh1, notND[1:0]);
  input [3:0] notNI;
  output sh1;
  output [1:0] notND ;

  ME_INV_A     i1 (notNI[1], NI1);
  ME_NAND2_B  i2 (NI1, notNI[2],   notBornotC);
  ME_AND2_B   i3 (notNI[3], notBornotC, sh1);
//  ME_INV_A  i1 (notNI[1], NI1);
//  ME_INV_A  i2 (notNI[3], NI3);
//  ME_A2O1I i3 (NI1, notNI[2], NI3, sh1);
  ME_AND2_B    r4 (notNI[0], notNI[1], notND[0] );
  ME_AND2_B    r5 (notNI[2], notNI[3], notND[1] );
endmodule


module onesch_sp (notNI[3:0], notsh1, notND[1:0]);
  input [3:0] notNI;
  output notsh1;
  output [1:0] notND ;

  ME_INV_A     i1 (notNI[1], NI1);
  ME_NAND2_B  i2 (NI1, notNI[2],   notBornotC);
  ME_NAND2_B  i3 (notNI[3], notBornotC, notsh1);
//  ME_INV_A  i1 (NI[2],             notNI2);
//  ME_O2A1I i2 (notNI[1], NI2, notNI[3], notsh1);
  ME_NAND2   r4 (notNI[0], notNI[1], notND[0] );
  ME_NAND2_B   r5 (notNI[2], notNI[3], notND[1] );
endmodule