/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 

module pci_add_mon ();

wire [31:0]     ad = Msystem.ad;
wire  [3:0]     cbe_ = Msystem.cbe_;
wire            par,     frame_, irdy_,    trdy_ ,
                 stop_,   lock_,  perr_,    serr_;

wire           devsel_  ;
wire            clock, rst_;

assign		frame_ = Msystem.frame_;
assign		irdy_ = Msystem.irdy_;
assign		trdy_ = Msystem.trdy_;
assign		stop_ = Msystem.stop_;
assign		lock_ = Msystem.lock_;
assign		perr_ = Msystem.perr_;
assign		serr_ = Msystem.serr_;

assign           devsel_  = Msystem.devsel_;

assign		clock = Msystem.pciClk0;
assign		rst_ = Msystem.reset_l;


reg	[31:0]	address;
reg     [31:0]  data;
reg	[3:0]	command;
reg	[7:0]	data_xfr_cnt;

reg		last_frame_;
reg		last_irdy_;
reg		address_enable_hold;
reg             data_xfr_hold;
reg             stop_xfr_hold;


`define INTERRUPT_ACKNOWLEDGE   4'b0000
`define SPECIAL_CYCLE           4'b0001
`define IO_READ                 4'b0010
`define IO_WRITE                4'b0011
`define PCI_RESERVED1           4'b0100
`define PCI_RESERVED2           4'b0101
`define MEMORY_READ             4'b0110
`define MEMORY_WRITE            4'b0111
`define PCI_RESERVED3           4'b1000
`define PCI_RESERVED4           4'b1001
`define CONFIGURATION_READ      4'b1010
`define CONFIGURATION_WRITE     4'b1011
`define MEMORY_READ_MULTIPLE    4'b1100
`define DUAL_ADDRESS_CYCLE      4'b1101
`define MEMORY_READ_LINE        4'b1110
`define MEMORY_WRITE_INVALIDATE 4'b1111

wire #1 address_enable = last_frame_ & ~frame_ & irdy_ & trdy_;

wire #1 end_xfr = ~last_irdy_ & irdy_ & frame_;

wire #1 data_xfr = ~devsel_ & ~irdy_ & ~trdy_;
wire #1 stop_xfr = ~devsel_ & ~irdy_ & ~stop_;

always @(posedge clock)
begin

last_frame_ <= #1 frame_;
last_irdy_ <= #1 irdy_;
address_enable_hold <= #1 address_enable;
data_xfr_hold <= #1 data_xfr;
stop_xfr_hold <= #1 stop_xfr;



if ((rst_ == 1'b0) || (address_enable == 1'b1))
  data_xfr_cnt = 8'h00;
else
  data_xfr_cnt <= data_xfr_cnt + data_xfr;

if (rst_ == 1'b0)
  begin
  address <= 32'h00000000;
  command <= 4'h0;
  end

else if (address_enable == 1'b1)
  begin
  address <= #1 ad;
  command <= #1 cbe_;
  end

if (rst_ == 1'b0)
  begin
    data = 32'h00000000;
  end
else if (data_xfr)
  data = #1 ad;
 

end


always @(posedge clock)
begin
if (address_enable_hold == 1'b1 )
  begin
        case(command)
 
        4'h0:   $displayh("\n PCI_ADD_MON: INT_ACK, address=",address);
        4'h1:   $displayh("\n PCI_ADD_MON: SPECIAL_CYCLE, address=",address);
        4'h2:   $displayh("\n PCI_ADD_MON: IO_RD, address=",address);
        4'h3:   $displayh("\n PCI_ADD_MON: IO_WRITE, address=",address);
        4'h4:   $displayh("\n PCI_ADD_MON: RESERVED1, address=",address);
        4'h5:   $displayh("\n PCI_ADD_MON: RESERVED2, address=",address);
        4'h6:   $displayh("\n PCI_ADD_MON: MEM_RD, address=",address);
        4'h7:   $displayh("\n PCI_ADD_MON: MEM_WRITE, address=",address);
        4'h8:   $displayh("\n PCI_ADD_MON: RESERVED3, address=",address);
        4'h9:   $displayh("\n PCI_ADD_MON: RESERVED4, address=",address);
        4'ha:   $displayh("\n PCI_ADD_MON: CONFIG_RD, address=",address);
        4'hb:   $displayh("\n PCI_ADD_MON: CONFIG_WRITE, address=",address);
        4'hc:   $displayh("\n PCI_ADD_MON: MEM_RD_MULTIPLE, address=",address);
        4'hd:   $displayh("\n PCI_ADD_MON: DUAL_ADDRESS, address=",address);
        4'he:   $displayh("\n PCI_ADD_MON: MEM_RD_LINE, address=",address);
        4'hf:   $displayh("\n PCI_ADD_MON: MEMORY_WRITE_INV, address=",address);
       endcase
  end
 
  else if (data_xfr_hold || stop_xfr_hold) 
   $displayh("\n PCI_ADD_MON: DATA_TRANSFER, data=",data,"  xfr_cnt=",data_xfr_cnt, " abort=",stop_xfr_hold);
end


endmodule