/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
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/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)pll.v 1.3 9/9/93
// Phase-Locked Loop Block.
module pll
(
input_clock,
pci_slave_mode,
pci_slave_mode_l,
ext_clk1,
ext_clk2,
pll_byp_l,
pci_feedback_clk,
// Added vdd and vss to PLL
pll_vdd,
pll_vss,
pll_rst,
pll_iiddtn
) ;
output input_clock
;
output pci_slave_mode
;
output pci_slave_mode_l
;
input ext_clk1
;
input ext_clk2
;
input pll_byp_l
;
input pci_feedback_clk
;
input pll_vdd
;
input pll_vss
;
input pll_rst
;
input pll_iiddtn
;
// Buffer ext_clk's (req )
wire ext_clk1_buf
;
wire ext_clk2_buf
;
wire pci_slave_mode;
wire pci_slave_mode_l;
// pci_slave_mode can only occur in non-bypass with ext_clk2 active
assign pci_slave_mode = ext_clk2 & pll_byp_l;
assign pci_slave_mode_l = ~pci_slave_mode;
buf (ext_clk1_buf, ext_clk1);
buf (ext_clk2_buf, ext_clk2);
buf (pci_feedback_clk_buf, pci_feedback_clk);
reg vco
;
// ext_clk1 is half the frequency of Mclocks.clock, with posedge
// coincident with a Mclocks.clock posedge.
// vco must be twice the frequency of Mclocks.clock .
// input_clock clocks the FF whose output is sys_clk. This FF has
// a ck->q of #1, and the clock distribution network has a delay of #2
// (see Bug 597). This code attempts to make sys_clk's
// edges coincident with those of Mclocks.clock .
// Simulated VCO - wait until ext_clk1 starts up, then
// generate a vco posedge #3 before each Mclocks.clock edge.
parameter
`ifdef PLL_PERIOD
EDGETIME = `PLL_PERIOD/2,
`else
EDGETIME = `CYCLETIME/4,
`endif
EDGE1 = (EDGETIME-3),
EDGE2 = ((2*EDGETIME)-3),
EDGE3 = ((3*EDGETIME)-3),
EDGE4 = ((4*EDGETIME)-3)
;
initial begin
vco = 0 ;
#1 forever @(ext_clk1) fork
#EDGE1 vco = 0 ;
#EDGE2 vco = 1 ;
#EDGE3 vco = 0 ;
#EDGE4 vco = 1 ;
join
end
// PLL will be connected to input_clock when the pll works correctly
wire pll_clkout
;
wire div4_q1
;
wire div4_q2
;
wire div4_d2
= ~div4_q1;
// Divide by 4 Counter
//Mflipflop_r div4_ff1 (div4_q1, div4_q2, pll_rst, pll_clkout);
//wire div4_d2 = ~div4_q1;
//Mflipflop_r div4_ff2 (div4_q2, div4_d2, pll_rst, pll_clkout);
Mflipflop_r div4_ff1 (.out(div4_q1) ,.in(div4_q2) ,.reset_l(pll_rst) ,.clock(pll_clkout));
Mflipflop_r div4_ff2 (.out(div4_q2) ,.in(div4_d2) ,.reset_l(pll_rst) ,.clock(pll_clkout));
//Change feedback clock on pll to be pci_feedback_clk buffered
//PLL300CBFI csl_pll ( pll_clkout, ext_clk1, div4_q2, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, pll_rst, pll_iiddtn, pll_vdd, pll_vss );
PLL300CBFI csl_pll ( pll_clkout, ext_clk1, pci_feedback_clk_buf
, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, pll_rst, pll_iiddtn, pll_vdd, pll_vss );
wire input_clock =
pll_byp_l ? vco
: (ext_clk1_buf ^ ext_clk2_buf)
;
endmodule
This page: |
Created: | Thu Aug 19 12:01:44 1999 |
| From: |
../../../sparc_v8/ssparc/pll/rtl/pll.v
|