// logic for constraint checking
not (NC1, C1);
and (TC_NC1, TC, NC1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: SRLC1C.v,v 1.2 1995/02/02 02:50:32 vdkmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module SRLC1C
(Q1, Q1N, Q2, Q2N, D, C1, SI, TC, C2);
output Q1
, Q1N
, Q2
, Q2N
;
input D
, C1
, SI
, TC
, C2
;
parameter
CMOS_TO_TTL = 0;
parameter
CLOAD$Q1 = 0;
parameter
CLOAD$Q1N = 0;
parameter
CLOAD$Q2 = 0;
parameter
CLOAD$Q2N = 0;
reg
notifier1
;
reg
notifier2
;
buf #(0.0, 0.0)
(Q1, Q1T);
buf #(0.0, 0.0)
(Q2, Q2T);
not #(0.0, 0.0)
(Q1N, Q1T);
not #(0.0, 0.0)
(Q2N, Q2T);
CSL_SRLC0
M1 (Q1T_int
, D, C1, SI, TC);
CSL_NOTI
(Q1T, Q1T_int, notifier1);
CSL_LD3
M2 (Q2T
, Q1T
, C2, 1, notifier2);
// logic for constraint checking
not (NC1, C1);
and (TC_NC1, TC, NC1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: PLL300CBFI.v,v 1.1 1996/09/20 00:18:26 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module PLL300CBFI
(CKOUT,REF,FB,HIGHFRQ,LOWFRQ,S2,S1,HR,EN,IDDTN,PLLVDD,PLLVSS);
output CKOUT
;
input REF
,FB
,HIGHFRQ
,LOWFRQ
,S2
,S1
,HR
,EN
,IDDTN
,PLLVDD
,PLLVSS
;
reg notifier
;
buf (PLLVDD_i, PLLVDD),
(PLLVSS_i, PLLVSS);
and (DUMMY1, S2,S1);
buf (DUMMY2, HIGHFRQ);
buf (DUMMY3, LOWFRQ);
buf (DUMMY4, HR);
CSL_FD3_Q u12 (S13
, 1'b1, REF, CD
, 1'b1, notifier);
CSL_FD3_Q u10 (S23
, 1'b1, FB, CD,1'b1, notifier);
not u14 (FBB, FB);
bufif1 u15 (S13A, S13, FB);
bufif1 u16 (S13A, S13, FBB);
bufif1 u17 (S23A, S23, FB);
bufif1 u18 (S23A, S23, FBB);
not u19 (REFB, REF);
bufif1 u20 (S13D, S13A, REF);
bufif1 u21 (S13D, S13A, REFB);
bufif1 u22 (S23D, S23A, REF);
bufif1 u23 (S23D, S23A, REFB);
nand u24 (CD1, S13D, S23D);
CSL_SPY u25 (CD2
, 1'b0, CD1
);
and u26 (CD, CD2, CD1);
bufif1 u27 (LP2_I, 1'b1, S13D);
bufif1 u28 (LP2_I, 1'b0, S23D);
nmos (LP2, LP2_I, 1'b1);
CSL_MUX21 (CKOUT_int, 1'b0, 1'bx, IDDTN);
and #(0.0, 0.0) (CKOUT, EN, CKOUT_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CSL_SPY.v,v 1.1 Exp $
primitive CSL_SPY
(o,a,fb);
output o
;
input a
,fb
;
table
// fb a : o
x 0 : 0;
x 1 : 1;
0 0 : 0;
0 1 : 1;
0 x : 0;
1 0 : 0;
1 1 : 1;
1 x : 1;
x x : x;
endtable
endprimitive
// $Header: CSL_FD3_Q.v,v 1.2 Exp $
![[Up: FD1QA M1]](v2html-up.gif)
![[Up: FD1QC M1]](v2html-up.gif)
![[Up: SCN4IMA M3]](v2html-up.gif)
![[Up: FD1SQA M1]](v2html-up.gif)
![[Up: FD1SQC M1]](v2html-up.gif)
![[Up: FD3QA M1]](v2html-up.gif)
![[Up: FD3QC M1]](v2html-up.gif)
![[Up: FDN1SQA M1]](v2html-up.gif)
![[Up: FDN1SQC M1]](v2html-up.gif)
![[Up: FD3SQA M1]](v2html-up.gif)
![[Up: FD3SQC M1]](v2html-up.gif)
![[Up: PLL300CBFI u12]](v2html-up.gif)
![[Up: PLL300CBFI u10]](v2html-up.gif)
![[Up: FD2ESSA M1]](v2html-up.gif)
![[Up: FD2ESSC M1]](v2html-up.gif)
![[Up: FDN2QA M1]](v2html-up.gif)
![[Up: FDN2QC M1]](v2html-up.gif)
![[Up: FD2QA M1]](v2html-up.gif)
![[Up: FD2QC M1]](v2html-up.gif)
![[Up: FD4QA M1]](v2html-up.gif)
![[Up: FD4QC M1]](v2html-up.gif)
![[Up: FD2SQA M1]](v2html-up.gif)
![[Up: FD2SQC M1]](v2html-up.gif)
![[Up: FDN2SQA M1]](v2html-up.gif)
![[Up: FDN2SQC M1]](v2html-up.gif)
![[Up: FD4SQA M1]](v2html-up.gif)
![[Up: FD4SQC M1]](v2html-up.gif)
![[Up: FDN1QA M1]](v2html-up.gif)
![[Up: FDN1QC M1]](v2html-up.gif)
![[Up: FD1SSOA M1]](v2html-up.gif)
![[Up: FD1SSOC M1]](v2html-up.gif)
... (truncated)
primitive CSL_FD3_Q
(Q, D, CP, CD, SD , notifier);
output Q
;
input D
, CP
, CD
, SD
, notifier
;
reg Q;
// Positive edge triggered D flip-flop with active low
// asynchronous set and clear. Clear dominates.
table
// D CP CD SD notifier : Qt : Qt+1
1 (01) 1 ? ? : ? : 1; // clocked data
0 (01) ? 1 ? : ? : 0; // clocked data
1 ? 1 * ? : 1 : 1; // pessimism
? 0 1 * ? : 1 : 1; // pessimism
? 1 1 * ? : 1 : 1; // pessimism
0 ? * 1 ? : 0 : 0; // pessimism
? 0 * 1 ? : 0 : 0; // pessimism
? 1 * 1 ? : 0 : 0; // pessimism
1 p 1 1 ? : 1 : 1; // reducing pessimism
0 p 1 1 ? : 0 : 0;
? ? 0 ? ? : ? : 0; // asynchronous clear
? ? 1 0 ? : ? : 1; // asynchronous set
? (?0) ? ? ? : ? : -; // ignore falling clock
0 (?x) ? ? ? : 0 : -; // retain state when D == Qt 1 (?x) ? ? ? : 1 : -; // retain state when D == Qt * 1 ? ? ? : ? : -; // ignore data edges
* 0 ? ? ? : ? : -; // ignore data edges
? ? ? ? * : ? : X;
endtable
endprimitive
// $Header: CSL_MUX21.v,v 1.2 Exp $
![[Up: SCN4IMA M1]](v2html-up.gif)
![[Up: SCN4IMA M2]](v2html-up.gif)
![[Up: FD1SQA M2]](v2html-up.gif)
![[Up: FD1SQC M2]](v2html-up.gif)
![[Up: FA1AA M1]](v2html-up.gif)
![[Up: FA1AB M1]](v2html-up.gif)
![[Up: FA1AC M1]](v2html-up.gif)
![[Up: FDN1SQA M2]](v2html-up.gif)
![[Up: FDN1SQC M2]](v2html-up.gif)
![[Up: FD3SQA M3]](v2html-up.gif)
![[Up: FD3SQC M3]](v2html-up.gif)
![[Up: FD2ESSA M2]](v2html-up.gif)
![[Up: FD2ESSC M2]](v2html-up.gif)
![[Up: DIFH2C M1]](v2html-up.gif)
![[Up: CSAHB M1]](v2html-up.gif)
![[Up: CSAHB M2]](v2html-up.gif)
![[Up: CSAHB M3]](v2html-up.gif)
![[Up: CSALB M1]](v2html-up.gif)
![[Up: CSALB M2]](v2html-up.gif)
![[Up: CSALB M3]](v2html-up.gif)
![[Up: FD2SQA M2]](v2html-up.gif)
![[Up: FD2SQC M2]](v2html-up.gif)
![[Up: FDN2SQA M2]](v2html-up.gif)
![[Up: FDN2SQC M2]](v2html-up.gif)
![[Up: FD4SQA M2]](v2html-up.gif)
![[Up: FD4SQC M2]](v2html-up.gif)
![[Up: FD1SSOA M2]](v2html-up.gif)
![[Up: FD1SSOC M2]](v2html-up.gif)
![[Up: FD1SSQA M2]](v2html-up.gif)
![[Up: FD1SSQA M3]](v2html-up.gif)
![[Up: FD1SSQC M2]](v2html-up.gif)
... (truncated)
primitive CSL_MUX21
(Q, A, B, SL);
output Q
;
input A
, B
, SL
;
// FUNCTION : TWO TO ONE MULTIPLEXER
table
// A B SL : Q
0 0 ? : 0 ;
1 1 ? : 1 ;
0 ? 0 : 0 ;
1 ? 0 : 1 ;
? 0 1 : 0 ;
? 1 1 : 1 ;
endtable
endprimitive
module IBUF
(z, po, a, pi);
output z
;
output po
;
input a
;
input pi
;
wire x
;
PREIBUF u1 (.Z(z) ,.PO(po) ,.A(x) ,.PI(pi));
IBUFDR d1 (.Z(x) ,.A(a));
endmodule
// $Header: L1DPLD1TSQ31FA.v,v 1.1 1996/07/23 17:09:22 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module L1DPLD1TSQ31FA
(QA,QB,QC,D,G,SA,SNA,SB,SNB,SC,SNC);
output QA
,QB
,QC
;
input D
,G
,SA
,SNA
,SB
,SNB
,SC
,SNC
;
reg notifier
;
CSL_LD3 (QT_int, D, G, 1'b1, notifier);
bufif1 (QA_int, QT_int, SA);
bufif0 (QA_int, QT_int, SNA);
nmos #(0.0,0.0) (QA, QA_int, 1'b1);
bufif1 (QB_int, QT_int, SB);
bufif0 (QB_int, QT_int, SNB);
nmos #(0.0,0.0) (QB, QB_int, 1'b1);
bufif1 (QC_int, QT_int, SC);
bufif0 (QC_int, QT_int, SNC);
nmos #(0.0,0.0) (QC, QC_int, 1'b1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: L1DPPGC.v,v 1.1 1996/06/27 23:55:38 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module L1DPPGC
(WEB,WE,CP);
output WEB
;
input WE
,CP
;
reg WEB_int
, notifier
;
initial
WEB_int = 1'b0;
buf (WE_int, WE);
buf (CP_int, CP);
always @ (posedge CP_int)
begin
if (WE_int == 1)
begin
#0.460 WEB_int = 1'b1 ;
#2.360 WEB_int = 1'b0 ;
end
end
always @ (notifier)
WEB_int = 1'bx;
buf (WEB, WEB_int);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CPRS32.v,v 1.1 1996/08/21 18:41:10 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CPRS32
(S,C,COUT,X1,X2,X3,CIN);
output S
,C
,COUT
;
input X1
,X2
,X3
,CIN
;
not (X1N, X1);
not (X2N, X2);
not (X3N, X3);
not (CINN, CIN);
and (X1X2, X1,X2);
CSL_MUX21 (Z2,X2N,X2,X1);
CSL_MUX21 (Z4,X3N,X3,Z2);
CSL_MUX21 #(0.0,0.0) (C,X1X2,CIN,Z4);
CSL_MUX21 #(0.0,0.0) (S,CIN,CINN,Z4);
or (CT0, X1,X2);
and #(0.0,0.0) (COUT, CT0,X3);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
// $Header: CPRS42P.v,v 1.1 1996/09/20 00:18:16 libmgr Exp $
`delay_mode_path
`suppress_faults
`enable_portfaults
`timescale 1 ns / 10 ps
`celldefine
module CPRS42P
(S,C,COUT,X1,X2,X3,X4,CIN);
output S
,C
,COUT
;
input X1
,X2
,X3
,X4
,CIN
;
not (X1N, X1);
not (X2N, X2);
not (X3N, X3);
not (X4N, X4);
not (CINN, CIN);
CSL_MUX21 (Z2N,X2N,X2,X1);
CSL_MUX21 (Z1N,X4N,X4,X3N);
not (Z1,Z1N);
and (AO1,X1,X2);
and (AO2,X3,X4);
or (C1N,AO1,AO2);
CSL_MUX21 (Z4N,Z1N,Z1,Z2N);
CSL_MUX21 #(0.0,0.0) (C,CIN,C1N,Z4N);
CSL_MUX21 #(0.0,0.0) (S,CINN,CIN,Z4N);
or (CT0, X1,X2);
or (CT1, X3,X4);
and #(0.0,0.0) (COUT, CT0,CT1);
endmodule
`endcelldefine
`nosuppress_faults
`disable_portfaults
This page: |
Created: | Thu Aug 19 12:01:34 1999 |
| From: |
../../../sparc_v8/lib/rtl/csl_lib.v
|