/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)ssparc.v
***
****************************************************************************
****************************************************************************/
//****************************************************************************
// ssparc.v
//
// Description:
// This is the top level module
//
//******************************************************************************
![[Up: Msystem ssparc]](v2html-up.gif)
module ssparc_chip
(
// delete standby for 2.0
// standby,
mc_memaddr, // memory address lines
mc_ras_l, // 8 RAS lines for DRAM
mc_cas_l, // 4 CAS outputs (word select)
mc_moe_l, // memory output enable
mc_mwe_l, // memory write enable
simm32_sel, // double density simm select
pci_clk0, // PCI reference clock
pci_clk1, // PCI reference clock
pci_clk2, // PCI reference clock
pci_clk3, // PCI reference clock
frame_l, // PCI FRAME#
trdy_l, // PCI TRDY#
irdy_l, // PCI IRDY#
stop_l, // PCI STOP#
devsel_l, // PCI DEVSEL#
pci_req_l, // PCI bus requests
pci_gnt_l, // PCI bus grants
ad, // PCI AD bus
cbe_l, // PCI CBE# bus
par, // PCI PAR bus
// pci_int_l should not be here
// instead use inta_, intb_, intc_, intd_
//pci_int_l, // PCI interrupt request lines
inta_, // PCI interrupt request lines
intb_,
intc_,
intd_,
// add the following for bidirects as additional interrupt lines
// in 2.0
inte_,
intf_,
intg_,
inth_,
perr_l, // PCI PERR#
serr_l, // PCI SERR#
pci_rst_l, // PCI RST#
// delete cp_stat_l from 2.0
// cp_stat_l, // level_15 interrupt/watchdog reset status
jtag_tdo, // JTAG test data out
b_memdata, // memory data bus (Bi-directional).
b_mempar, // memory parity bus (Bi-directional).
//Flash Prom IO additions:
rom_oe_l,
rom_we_l,
rom_addr,
rom_cs_l,
div_ctl, // PCI bus clock control
sp_sel, // 70/85/100/125MHz (Lo/Hi) speed select i/p
bm_sel, // bm sel 00 = 32 bit afx flash
// 01 = 8 bit afx flash
// 10 = pci cheerio f000.0000
// 11 = pci super io fffe.0000
jtag_ck, // JTAG clock
jtag_ms, // JTAG mode select
jtag_tdi, // JTAG test data in
jtag_trst_l, // Jtag reset in
ext_clk1,
ext_clk2,
pll_byp_l,
input_reset_l,
int_event_l, // Output to external clock counter
ext_event_l, // Input from external clock counter
ref_clk, // swift internal reference clock
// csl test and pll signals
iiddtn, // csl iiddtn
csl_scan_mode, // csl scan mode,
pll_vdd, // pll vdd
pll_vss, // pll vss
procmon, // csl procomon
pll_rst, // pll_rst
// 2 more inputs added
tn, // goes to the TN port of bidi and outputs
therm_d // thermal diode pin
);
input iiddtn; // csl iiddtn
input csl_scan_mode; // csl scan mode
// Changed pll_vdd and pll_vss to inputs
//inout pll_vdd; // pll_vdd
//inout pll_vss; // pll_vss
input pll_vdd; // pll_vdd
input pll_vss; // pll_vss
input pll_rst; // pll_rst - don't know functionality??
output procmon; // process monitor
input tn;
input therm_d;
input ext_clk1 ; // PLL ref clock, or XOR term of external clock
input ext_clk2 ; // 2nd XOR term of external clock
input pll_byp_l ; // Use (ext_clk1 XOR ext_clk2) instead of PLL
// input standby ; // Low-power-mode request
output [11:0] mc_memaddr; // memory address lines
output [7:0] mc_ras_l; // 8 RAS lines for DRAM
output [3:0] mc_cas_l; // 4 CAS outputs (word select)
output mc_moe_l; // memory output enable
output mc_mwe_l; // memory write enable
output pci_clk0; // PCI reference clock
output pci_clk1; // PCI reference clock
output pci_clk2; // PCI reference clock
output pci_clk3; // PCI reference clock
inout frame_l; // PCI FRAME#
inout trdy_l; // PCI TRDY#
inout irdy_l; // PCI IRDY#
inout stop_l; // PCI STOP#
inout devsel_l; // PCI DEVSEL#
inout perr_l; // PCI PERR#
inout serr_l; // PCI SERR#
input [3:0] pci_req_l; // PCI bus requests
output [3:0] pci_gnt_l; // PCI bus grants
inout [31:0] ad; // PCI AD bus
inout [3:0] cbe_l; // PCI CBE# bus
inout par; // PCI PAR bus
//input [3:0] pci_int_l; // PCI interrupt request lines
// change the interrupt lines to inout
// all interrupt lines are open drain now
inout inta_; // PCI interrupt request lines
inout intb_;
inout intc_;
inout intd_;
// add the 4 interrupts below:
inout inte_;
inout intf_;
inout intg_;
inout inth_;
//Modified div_ctl to 2 bit bus
input [1:0] div_ctl; // PCI clock control
output pci_rst_l; // PCI RST#
// output [1:0] cp_stat_l; // level_15 interrupt/watchdog reset status
output jtag_tdo; // JTAG test data out
output int_event_l ; // output to external clock counter
output ref_clk ; // swift internal reference clock
//PROM outputs:
output rom_oe_l;
output rom_we_l;
output [23:0] rom_addr;
output rom_cs_l;
inout [63:0] b_memdata; // memory word data bits
inout [1:0] b_mempar; // memory word parity bits
input simm32_sel; // double density simm
input [2:0] sp_sel; // 70/85/100/125MHz (Lo/Hi) speed select i/p
// add sp_sel[2] for 150Mhz - 200 Mhz.
input [1:0] bm_sel; // afx /pci boot select pins
input jtag_ck; // JTAG clock
input jtag_ms; // JTAG mode select
input jtag_tdi; // JTAG test data in
input jtag_trst_l; // primary input reset pin to the jtag block
input input_reset_l; // input reset from Macio
input ext_event_l ; // input from external clock counter
// Constants, driven by cells in misc block
wire logic_0 ; // clk_misc => ssparc_core
wire logic_1 ; // clk_misc => <nowhere>
wire [7:0] w_ext_int_oe;
// add wires for the 2.0 reset cleanup
// assign the sw_rst to 0 until stuff is ready
wire sw_rst ;
wire en_sw_rst_nonwd ;
wire en_pci_sw_rst ;
wire pci_slave_mode;
wire pci_slave_mode_l;
wire pci_rst_pin_out_l;
wire pci_rst_pin_in_l;
wire pci_rst_int_l;
// Removed these as per request and put them in clk_misc
// Also instantiated 2 more scan chains in clk_misc using bm_sel and cp_stat_l
//wire w_csl_scan_mode;
//wire w_jtag_tdi, w_jtag_tdo, w_jtag_ms;
//wire csl_scan_out1, csl_scan_out2;
//wire procmon_out;
// define the csl_scan inputs for the 2 scan chains.
//wire csl_scan_in1 = w_jtag_tdi;
//wire csl_scan_in2 = w_jtag_ms;
//wire w_jtag_tdo_scan_out1 = w_csl_scan_mode ? csl_scan_out1 : w_jtag_tdo;
//wire w_procmon = w_csl_scan_mode ? csl_scan_out2 : procmon_out;
// End modifications
wire [1:0] w_bm_sel; // io => ssparc_core
// standby_dsbl_tlb active in the ref_clk cycles when ss_clock is disabled,
// but not in the last sbclk cycle of this period.
wire standby_dsbl_tlb ; // clk_misc => ssparc_core
wire iu_error_l; // clk_misc => io
wire any_intrnl_int_l; // ssparc_core => io/w_cp_stat_l[0]
wire pcic_idle; // Will be connected to Clock Controller
wire go_standby; // qualified OR of pin or programmable bit
/* pcic wires ****************/
//wire intd_ = pci_int_l[3]; // PCI interrupt line
//wire intc_ = pci_int_l[2]; // PCI interrupt line
//wire intb_ = pci_int_l[1]; // PCI interrupt line
//wire inta_ = pci_int_l[0]; // PCI interrupt line
wire w_pci_rst_l; // pci reset, synch to pci_clk
// include this temporarily for the afx_mon from phoenix
wire w_mc_moe_l; //
wire w_mc_mwe_l;
wire reset;
wire tmr_clk; // divide by 4 to generate timer clock.
wire gclk_unbuf;
wire gclk_unbuf_;
wire pci_refclk_unbuf;
wire pci_refclk_unbuf_;
wire pci_clk0 ;
wire pci_clk1 ;
wire pci_clk2 ;
wire pci_clk3 ;
// wires for the IO connections
// end Ravicad declarations from Ravicad's system.v
// This wire is assigned in task.v so that we can still do standby testing
wire w_standby ;
/****************************************************************************/
// Now instantiate the io pads
wire bscan_sel_ff ; // (forward)
wire bscan_sel_ff_in = bscan_sel_ff ;
wire bscan_sel_ff_out = bscan_sel_ff ;
/* scan connection nets declared here - defines scan chain too*/
wire isr_tdi ;
wire rl_memif_scan_out ;
/* */
/***************** IU model ********************************************************/
/* */
/***************** Cache RAM models ****************************************/
// These 2 don't go any where presently. They are needed for asi tag reads.
// Remember to connect them to rl_dc_cntl.
/********* MMU model ********************************************************/
//
// PROM speed signal- new
// i've connected pipe_hold4mmu_cntl to the iu_pipe_hold port
// here. i also have one ready for the DP. (pipe_hold4mmu_dp).
// -- arthur
/* ^L */
/***************** PROMIF model **************************************/
/*-------- start of mkiopads output --------*/
// Automatically generated from iopad_order rev 1.9 by mkiopads, rev 1.9
// (see iopads.v for pin assignments)
wire ss_clock ;
wire [31:0] ad, w_ad_out, w_ad_in ;
wire [63:0] b_memdata, w_b_memdata_out, w_b_memdata_in ;
wire [1:0] b_mempar, w_b_mempar_out, w_b_mempar_in ;
wire [3:0] cbe_l, w_cbe_out, w_cbe_in ;
//wire [1:0] cp_stat_l, w_cp_stat_l ;
//wire [1:0] w_cp_stat_l ;
wire [1:0] div_ctl, w_div_ctl ;
wire [3:0] mc_cas_l, w_mc_cas_l ;
wire [11:0] mc_memaddr, w_mc_memaddr ;
wire [7:0] mc_ras_l, w_mc_ras_l ;
wire [3:0] pci_gnt_l, w_pci_gnt_l ;
wire [3:0] pci_req_l, w_pci_req_l ;
wire [23:0] rom_addr, w_rom_addr ;
wire [2:0] sp_sel, w_sp_sel ;
wire simm32_sel, w_simm32_sel ;
wire w_pll_vdd, w_pll_vss, w_pll_rst ;
wire w_procmon, w_csl_scan_mode, w_tn_po ;
wire w_iiddtn, w_tn, w_therm_d ;
wire parametric_out ;
wire csl_scan_out1, csl_scan_out2, csl_scan_out3, csl_scan_out4 ;
wire w_rom_oe_ls, w_rom_cs_ls ;
// Moved this to clk_misc
//assign w_cp_stat_l[1:0] = {iu_error_l, any_intrnl_int_l};
iopads ssparc_iopads(
// test and pll special connections:
.pll_vdd (pll_vdd),
// Added pll vdd and vss outputs
.w_pll_vdd (w_pll_vdd),
.pll_vss (pll_vss),
.w_pll_vss (w_pll_vss),
.pll_rst (pll_rst),
.w_pll_rst (w_pll_rst),
.procmon (procmon),
.w_procmon (parametric_out),
// added for procmon
.procmon_e (w_tn_po),
// .procmon_s (w_csl_scan_mode & w_jtag_trst_l),
// Changed to not scan mode for 1.0
.procmon_s (~w_csl_scan_mode ),
// scan output is on pin n
.procmon_n (1'b0),
.procmon_sel (w_csl_scan_mode),
.procmon_csl_scan (w_procmon),
.csl_scan_mode (csl_scan_mode),
.w_csl_scan_mode (w_csl_scan_mode),
.iiddtn (iiddtn),
.w_iiddtn (w_iiddtn),
.tn (tn),
.w_tn (w_tn),
.w_tn_po (w_tn_po),
// this is where w_tn goes back to the TN port of bidi's and outputs
.w_input_tn (w_tn),
.therm_d (therm_d),
.w_therm_d (w_therm_d),
// this is the output of the parametric chain and goes to the "a" pin of the procmon
.po_out (parametric_out),
.pci_clk0_oen (1'b1), // using bidi, output always enabled
.pci_clk1_oen (1'b1), // using bidi, output always enabled
.pci_clk2_oen (1'b1), // using bidi, output always enabled
.pci_clk3_oen (1'b1), // using bidi, output always enabled
.w_pci_clk0_out (pci_refclk_unbuf),
.w_pci_clk1_out (pci_refclk_unbuf),
.w_pci_clk2_out (pci_refclk_unbuf),
.w_pci_clk3_out (pci_refclk_unbuf),
.pci_clk0 (pci_clk0),
.pci_clk1 (pci_clk1),
.pci_clk2 (pci_clk2),
.pci_clk3 (pci_clk3),
.pci_req_oen (1'b0), // using bidi, input always, drive disabled
.pci_gnt_oen (w_input_reset_l), // using bidi, output disabled when pci is reset
.inta_oen (w_ext_int_oe[0]), // using bidi, input always, drive disabled
.intb_oen (w_ext_int_oe[1]), // using bidi, input always, drive disabled
.intc_oen (w_ext_int_oe[2]), // using bidi, input always, drive disabled
.intd_oen (w_ext_int_oe[3]), // using bidi, input always, drive disabled
// change for 2.0 reset cleanup, only drive in pci master mode
// .pci_rst_oen (1'b1), // using bidi, output always, enabled
.pci_rst_oen (pci_slave_mode_l), // using bidi, output always, enabled
.simm32_sel (simm32_sel),
.w_simm32_sel (w_simm32_sel),
.ADEnable (ADEnable),
.PAREnable (PAREnable),
.ad (ad[31:0]),
.w_ad_out (w_ad_out[31:0]),
.w_ad_in (w_ad_in[31:0]),
.b_mem_oen (b_mem_oen),
.b_memdata (b_memdata[63:0]),
.w_b_memdata_out (w_b_memdata_out[63:0]),
.w_b_memdata_in (w_b_memdata_in[63:0]),
.b_mempar (b_mempar[1:0]),
.w_b_mempar_out (w_b_mempar_out[1:0]),
.w_b_mempar_in (w_b_mempar_in[1:0]),
.bscan_clk_cap (cap_shft_clk),
.bscan_clk_upd (bscan_clk_upd),
.bscan_shift (bscan_mode),
.bscan_sel_ff_in (bscan_sel_ff_in),
.bscan_sel_ff_out (bscan_sel_ff_out),
.cbe (cbe_l[3:0]),
.w_cbe_out (w_cbe_out[3:0]),
.w_cbe_in (w_cbe_in[3:0]),
.cbeEnable (cbeEnable),
// .cp_stat_l (cp_stat_l[1:0]),
// .w_cp_stat_l (w_cp_stat_l[1:0]),
.inte_ (inte_),
// must be left as 0 for open drain
.w_inte__out (1'b0),
.w_inte__in (w_inte_),
.inte_oen (w_ext_int_oe[4]),
.intf_ (intf_),
// must be left as 0 for open drain
.w_intf__out (1'b0),
.w_intf__in (w_intf_),
.intf_oen (w_ext_int_oe[5]),
.intg_ (intg_),
// must be left as 0 for open drain
.w_intg__out (1'b0),
.w_intg__in (w_intg_),
.intg_oen (w_ext_int_oe[6]),
.inth_ (inth_),
// must be left as 0 for open drain
.w_inth__out (1'b0),
.w_inth__in (w_inth_),
.inth_oen (w_ext_int_oe[7]),
.devselEn (devselEn),
.devsel_l (devsel_l),
.w_devsel_l_out (w_devsel_l_out),
.w_devsel_l_in (w_devsel_l_in),
.div_ctl (div_ctl[1:0]),
.w_div_ctl (w_div_ctl[1:0]),
.ext_clk1 (ext_clk1),
.w_ext_clk1 (w_ext_clk1),
.ext_clk2 (ext_clk2),
.w_ext_clk2 (w_ext_clk2),
.ext_event_l (ext_event_l),
.w_ext_event_l (w_ext_event_l),
.frameEn (frameEn),
.frame_l (frame_l),
.w_frame_l_out (w_frame_l_out),
.w_frame_l_in (w_frame_l_in),
.input_reset_l (input_reset_l),
.w_input_reset_l (w_input_reset_l),
.int_event_l (int_event_l),
.w_int_event_l (w_int_event_l),
.inta_ (inta_),
// must be left as 0 for open drain
.w_inta__out(1'b0),
.w_inta__in (w_inta_),
.intb_ (intb_),
// must be left as 0 for open drain
.w_intb__out(1'b0),
.w_intb__in (w_intb_),
.intc_ (intc_),
// must be left as 0 for open drain
.w_intc__out(1'b0),
.w_intc__in (w_intc_),
.intd_ (intd_),
// must be left as 0 for open drain
.w_intd__out(1'b0),
.w_intd__in (w_intd_),
.irdyEn (irdyEn),
.irdy_l (irdy_l),
.w_irdy_l_out (w_irdy_l_out),
.w_irdy_l_in (w_irdy_l_in),
.jtag_ck (jtag_ck),
.w_jtag_ck (w_jtag_ck),
.jtag_ms (jtag_ms),
.w_jtag_ms (w_jtag_ms),
.jtag_tdi (jtag_tdi),
.w_jtag_tdi (w_jtag_tdi),
.jtag_tdo (jtag_tdo),
.w_jtag_tdo (w_jtag_tdo_scan_out1),
.jtag_tdo_oen_l (jtag_tdo_oen_l), // Active-low enable for jtag_tdo
.jtag_trst_l (jtag_trst_l),
.w_jtag_trst_l (w_jtag_trst_l),
.mc_cas_l (mc_cas_l[3:0]),
.w_mc_cas_l (w_mc_cas_l[3:0]),
.mc_memaddr (mc_memaddr[11:0]),
.w_mc_memaddr (w_mc_memaddr[11:0]),
.mc_moe_l (mc_moe_l),
.w_mc_moe_l (w_mc_moe_l),
.mc_mwe_l (mc_mwe_l),
.w_mc_mwe_l (w_mc_mwe_l),
.mc_ras_l (mc_ras_l[7:0]),
.w_mc_ras_l (w_mc_ras_l[7:0]),
.par (par),
.w_par_out (w_par_out),
.w_par_in (w_par_in),
.pci_gnt_l (pci_gnt_l[3:0]),
.w_pci_gnt_l_out (w_pci_gnt_l[3:0]),
.pci_req_l (pci_req_l[3:0]),
.w_pci_req_l_in (w_pci_req_l[3:0]),
.pci_rst_l (pci_rst_l),
// change this in 2.0
// .w_pci_rst_l_out (w_input_reset_l),
.w_pci_rst_l_out (pci_rst_pin_out_l),
.w_pci_rst_l_in (pci_rst_pin_in_l),
.perrEn (perrEn),
.perr_l (perr_l),
.w_perr_l_out (w_perr_l_out),
.w_perr_l_in (w_perr_l_in),
.pll_byp_l (pll_byp_l),
.w_pll_byp_l (w_pll_byp_l),
.ref_clk (ref_clk),
.w_ref_clk (ss_clock), // reconnected w_ref_clk to ss_clock
.rom_addr (rom_addr[23:0]),
.w_rom_addr (w_rom_addr[23:0]),
.rom_cs_l (rom_cs_l),
.w_rom_cs_l (w_rom_cs_ls),
.rom_oe_l (rom_oe_l),
.w_rom_oe_l (w_rom_oe_ls),
.rom_we_l (rom_we_l),
.w_rom_we_l (w_rom_we_l),
.serrEnable (serrEnable),
.serr_l (serr_l),
.w_serr_l_out (w_serr_l_out),
.w_serr_l_in (w_serr_l_in),
.sp_sel (sp_sel[2:0]),
.w_sp_sel (w_sp_sel[2:0]),
.bm_sel (bm_sel[1:0]),
.w_bm_sel (w_bm_sel[1:0]),
// .standby (standby),
// .w_standby (w_standby),
.stopEn (stopEn),
.stop_l (stop_l),
.w_stop_l_out (w_stop_l_out),
.w_stop_l_in (w_stop_l_in),
.trdyEn (trdyEn),
.trdy_l (trdy_l),
.w_trdy_l_out (w_trdy_l_out),
.w_trdy_l_in (w_trdy_l_in),
.scan_out (iopads_scan_out)
) ;
/*-------- end of mkiopads output --------*/
/* */
/***************** clk_cntl and misc ************************/
clk_misc clk_misc(
.bscan_clk_a (bscan_clk_a),
.bscan_clk_b (bscan_clk_b),
.bscan_clk_upd (bscan_clk_upd),
.bscan_clk_cap (bscan_clk_cap),
.bscan_sel_ff (bscan_sel_ff),
.bscan_mode (bscan_mode),
.pll_byp_l (w_pll_byp_l),
.cap_shft_clk (cap_shft_clk),
.gclk_1st_phase (gclk_1st_phase),
.memif_idle (memif_idle),
.pcic_idle (pcic_idle),
.ic_standby_f (ic_standby_f),
.dc_standby_w (dc_standby_w),
.standby_dsbl_tlb (standby_dsbl_tlb),
.standby_req (standby_req),
.reset_iu (reset_iu),
.reset (reset),
.ss_scan_mode (ss_scan_mode),
.tg_strobe (tg_strobe),
.jtag_tdo (w_jtag_tdo),
.jtag_tdo_oen_l (jtag_tdo_oen_l),
.int_event_l (w_int_event_l),
.ss_clock_unbuf (ss_clock), // bypass all buffers
.rfr_clock_unbuf (rfr_clock), // bypass all buffers
.rfr_late_unbuf (rfr_late), // bypass all buffers
.rcc_clk_unbuf (rcc_clk), // bypass all buffers
.pci_refclk_unbuf (pci_refclk_unbuf),
.pci_refclk_unbuf_ (pci_refclk_unbuf_),
.tmr_clk (tmr_clk),
.gclk_unbuf (gclk_unbuf), // bypass buffers. rename w_gclk
.gclk_unbuf_ (gclk_unbuf_),
.sboclk_unbuf (sboclk), // bypass all buffers
//.sbus_clk_unbuf (w_sbclk), // bypass all buffers
.standby (go_standby),
.div_ctl (w_div_ctl[1:0]),
.jtag_ck (w_jtag_ck),
.jtag_ms (w_jtag_ms),
.jtag_tdi (w_jtag_tdi),
.jtag_trst_l (w_jtag_trst_l),
// Begin additions
.csl_scan_out1 (csl_scan_out1),
.csl_scan_out2 (csl_scan_out2),
.csl_scan_out3 (csl_scan_out3),
.csl_scan_out4 (csl_scan_out4),
.csl_scan_mode (w_csl_scan_mode),
//.csl_scan_in1 (w_jtag_tdi),
//.csl_scan_in2 (w_jtag_ms),
//.csl_scan_in3 (w_bm_sel[0]),
//.csl_scan_in4 (w_bm_sel[1]),
.w_jtag_tdo_scan_out1 (w_jtag_tdo_scan_out1),
.w_procmon (w_procmon),
// .w_cp_stat_l (w_cp_stat_l),
// .any_intrnl_int_l (any_intrnl_int_l),
.w_rom_oe_l (w_rom_oe_l),
.w_rom_cs_l (w_rom_cs_l),
.w_rom_oe_ls (w_rom_oe_ls),
.w_rom_cs_ls (w_rom_cs_ls),
// End addtions
.input_reset_l (w_input_reset_l),
// add the following for 2.0 reset cleanup
.sw_rst (sw_rst),
.en_sw_rst_nonwd (en_sw_rst_nonwd),
.pci_slave_mode (pci_slave_mode),
.pci_rst_pin_out_l (pci_rst_pin_out_l),
.pci_rst_int_l (pci_rst_int_l),
.en_pci_sw_rst (en_pci_sw_rst),
.pci_rst_pin_in_l (pci_rst_pin_in_l),
.ext_event_l (w_ext_event_l),
.ss_misc_scan_in (rl_memif_scan_out),
.isr_tdi (isr_tdi),
.bsr_tdo (iopads_scan_out),
.iu_error (iu_error),
.iu_error_l (iu_error_l),
.mm_hold_rst (mm_hold_rst),
.mm_event (mm_bp_dtct),
.iu_event (iu_event),
.first_phi (first_phi),
.next2last_phi (next2last_phi),
.last_phi (last_phi),
.logic_0 (logic_0),
.logic_1 (logic_1),
.rcc_clk (rcc_clk),
.input_clock (input_clock)
) ;
// Phase-Locked Loop Block
// Added vdd, vss, rst and iiddtn to PLL
pll pll (
.input_clock (input_clock),
.ext_clk1 (w_ext_clk1),
.ext_clk2 (w_ext_clk2),
.pll_byp_l (w_pll_byp_l),
// add for 2.0 reset cleanup
.pci_slave_mode (pci_slave_mode),
.pci_slave_mode_l (pci_slave_mode_l),
// The pci feedback clock must be run throught the balanced clock tree
// and adjusted to any setup / hold time tolerances. Need to be careful
// with loading.
.pci_feedback_clk (pci_refclk_unbuf),
.pll_vdd (w_pll_vdd),
.pll_vss (w_pll_vss),
.pll_rst (w_pll_rst),
.pll_iiddtn (w_iiddtn)
) ;
/**************************************************************************/
ssparc_core ssparc_core (
// added iiddtn to turn off the caches and tags during IDDQ test
.iiddtn (w_iiddtn),
// added 4 scan chains to meet requirements for Internal scan chain
.csl_scan_in1 (w_jtag_tdi),
.csl_scan_in2 (w_sp_sel[2]),
.csl_scan_in3 (w_bm_sel[0]),
.csl_scan_in4 (w_bm_sel[1]),
// .csl_scan_in1 (csl_scan_in1),
// .csl_scan_in2 (csl_scan_in2),
// .csl_scan_in3 (csl_scan_in3),
// .csl_scan_in4 (csl_scan_in4),
.csl_scan_out1 (csl_scan_out1),
.csl_scan_out2 (csl_scan_out2),
.csl_scan_out3 (csl_scan_out3),
.csl_scan_out4 (csl_scan_out4),
// end
.tg_strobe(tg_strobe),
.ss_scan_mode( w_csl_scan_mode),
.csl_scan_mode( w_csl_scan_mode),
.logic_0(logic_0),
.ss_clock(ss_clock),
.standby_req( standby_req),
.ic_standby_f(ic_standby_f),
.dc_standby_w(dc_standby_w),
.reset(reset),
.reset_iu(reset_iu),
.iu_error(iu_error),
.iu_event( iu_event),
.w_mc_ras_l( w_mc_ras_l[7:0] ),
.w_mc_cas_l( w_mc_cas_l[3:0] ),
.w_s_reply(),
.w_mc_moe_l(w_mc_moe_l),
.w_mc_mwe_l(w_mc_mwe_l),
.w_simm32_sel(w_simm32_sel),
.rl_memif_scan_out(rl_memif_scan_out),
.memif_idle(memif_idle),
.w_aen(),
.w_b_mempar_in( w_b_mempar_in[1:0]),
.w_sp_sel(w_sp_sel[2:0]),
.rfr_clock(rfr_clock),
.rfr_late(rfr_late),
.gclk_1st_phase(gclk_1st_phase),
.w_p_reply(2'b00),
.mm_bp_dtct(mm_bp_dtct),
.mm_hold_rst(mm_hold_rst),
.any_intrnl_int_l(any_intrnl_int_l),
.w_bm_sel(w_bm_sel[1:0]),
.w_div_ctl(w_div_ctl[1:0]),
.standby_dsbl_tlb(standby_dsbl_tlb),
.w_pci_req_l(w_pci_req_l[3:0]),
.w_ext_int_({w_inth_,w_intg_,w_intf_,w_inte_,w_intd_, w_intc_, w_intb_, w_inta_}),
.w_ext_int_oe(w_ext_int_oe[7:0]),
.w_pci_gnt_l(w_pci_gnt_l[3:0]),
.tmr_clk(tmr_clk ),
.w_gclk(gclk_unbuf ),
.w_b_memdata_in(w_b_memdata_in[63:0]),
.w_ab_out(),
.w_mc_memaddr(w_mc_memaddr[11:0]),
.ADEnable(ADEnable),
.cbeEnable(cbeEnable),
.PAREnable(PAREnable),
.frameEn(frameEn),
.trdyEn(trdyEn),
.irdyEn(irdyEn),
.stopEn(stopEn),
.devselEn(devselEn),
.perrEn(perrEn),
.serrEnable(serrEnable),
.w_ad_out(w_ad_out[31:0]),
.w_cbe_out(w_cbe_out[3:0]),
.w_par_out(w_par_out),
.w_frame_l_out(w_frame_l_out),
.w_trdy_l_out( w_trdy_l_out),
.w_irdy_l_out(w_irdy_l_out),
.w_stop_l_out(w_stop_l_out ),
.w_devsel_l_out(w_devsel_l_out),
.w_serr_l_out(w_serr_l_out),
.w_perr_l_out(w_perr_l_out),
.w_ad_in(w_ad_in[31:0]),
.w_cbe_in(w_cbe_in[3:0]),
.w_par_in(w_par_in),
.w_frame_l_in(w_frame_l_in),
.w_irdy_l_in( w_irdy_l_in),
.w_perr_l_in(w_perr_l_in),
.w_serr_l_in(w_serr_l_in),
.w_trdy_l_in(w_trdy_l_in),
.w_stop_l_in(w_stop_l_in),
.w_devsel_l_in( w_devsel_l_in),
// change this for 2.0 to allow input reset, s/w rest
// .w_pci_rst_l(w_pci_rst_l),
.pci_rst_int_l(pci_rst_int_l),
.pci_clk(pci_refclk_unbuf),
.pci_clk_(pci_refclk_unbuf_ ),
.pci_clk_sync(pci_refclk_unbuf),
.pci_clk_sync_(pci_refclk_unbuf_),
.gclk_sync(gclk_unbuf),
.gclk_sync_(gclk_unbuf_),
.b_mem_oen(b_mem_oen),
.w_b_memdata_out(w_b_memdata_out[63:0]),
.w_b_mempar_out(w_b_mempar_out[1:0]),
.w_rom_addr(w_rom_addr[23:0]),
.w_rom_oe_l(w_rom_oe_l),
.w_rom_we_l(w_rom_we_l),
.w_rom_cs_l(w_rom_cs_l),
.pcic_idle(pcic_idle),
.go_standby(go_standby),
.pin_go_standby(w_standby),
.isr_tdi(isr_tdi),
.last_phi(last_phi),
.next2last_phi(next2last_phi),
.first_phi(first_phi),
.sw_rst(sw_rst),
.en_sw_rst_nonwd(en_sw_rst_nonwd),
.en_pci_sw_rst(en_pci_sw_rst),
.pci_slave_mode(pci_slave_mode),
.input_reset_l(w_input_reset_l),
.pci_rst_pin_in_l(pci_rst_pin_in_l),
.sboclk(sboclk) );
endmodule
| This page: |
Created: | Thu Aug 19 12:03:22 1999 |
| From: |
../../../sparc_v8/ssparc/rtl/ssparc.v
|