/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
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/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)retry_sm.v
***
***
*** Description:
*** This is the afxmaster state machine for generating
*** the 'force_pci_retry' signal to the pci slave during
*** retry conditions.
***
****************************************************************************
****************************************************************************/
`define RETRY_IDLE 3'b000
`define SAVE_ADDR 3'b001
`define RETRY 3'b011
`define DISCARD_CHK 3'b010
`define DISCARD_TO 3'b110
`timescale 1ns/1ns
module retry_sm
(force_pci_retry, save_addr, discard_timeout,
pclk, reset_l, flush_stale_read, cmd_start, cmd_start1,
pci_mem_rd, pci_mem_wrt ,
delayed_read, idle_cyc, write_fifos_empty,
tar_xmt_fifo_empty, retry_addr_match, read_pack_done,
ack_quiescence, discard_timer, discard_ok);
output force_pci_retry
; // signal to pci_slave to retry initiator
output save_addr
; // save retried address
output discard_timeout
; // read discard timeout = true
input pclk
; // pci clk
input reset_l
; // system or PCI reset_l
input flush_stale_read
; // flush a stale read
input cmd_start
; // pci cmd valid
input cmd_start1
; // delayed pci cmd valid
input pci_mem_rd
; // pci cmd is memory read
input pci_mem_wrt
; // pci cmd is memory write
input delayed_read
; // afxm delayed read flag
input idle_cyc
; // afxm_sm idle cyc in pclk domain
input write_fifos_empty
; // tar_rcv fifos empty
input tar_xmt_fifo_empty
; // tar_xmit (read) fifo empty
input retry_addr_match
; // accept retry only if address match
// retried address
input read_pack_done
; // xmit fifos packed sufficiently
input ack_quiescence
; // falcon status reg bit indicating a
// 'flush write buffers request' from cpu
wire [2:0] retry_state
; // curr state of retry sm
input [14:0] discard_timer
; // discard timer timeout max (from config reg @0x68)
input discard_ok
; // ok to discard read data afxm read done
wire [14:0] discard_count
; // discard counter for unclaimed read data timeout
function [17:0] force_retry_sm;
input [2:0] retry_state;
input reset_l; // system or PCI reset_l
input flush_stale_read; // flush stale read data
input cmd_start; // pci cmd valid
input cmd_start1; // delayed pci cmd valid
input pci_mem_rd; // pci cmd is memory read
input pci_mem_wrt; // pci cmd is memory write
input delayed_read; // afxm delayed read flag
input idle_cyc; // afxm_sm idle cyc in pclk domain
input write_fifos_empty; // tar_rcv fifos empty
input tar_xmt_fifo_empty; // tar_xmit (read) fifo empty
// retried address
input retry_addr_match; // accept retry only if address match
input read_pack_done; // xmit fifos packed sufficiently
input ack_quiescence; // falcon status reg bit indicating a
// 'flush write buffers request' from cpu
input [14:0] discard_count; // running discard counter for unclaimed read data timeout
input [14:0] discard_timer; // discard timer timeout max (from config reg @0x68)
input discard_ok; // ok to discard read data afxm read done
reg [2:0] retry_ns; // next_state
reg [14:0] discard_cnt; // next discard count value
begin
if (~reset_l || flush_stale_read) begin
retry_ns = `RETRY_IDLE;
discard_cnt = discard_timer;
end
else begin
retry_ns = retry_state;
discard_cnt = discard_count;
case (retry_state)
`RETRY_IDLE: begin
discard_cnt = discard_count;
if (cmd_start & ~cmd_start1 & pci_mem_rd & ~delayed_read &
write_fifos_empty & tar_xmt_fifo_empty)
retry_ns = `SAVE_ADDR;
else
retry_ns = `RETRY_IDLE;
end
`SAVE_ADDR: begin
retry_ns = `RETRY;
end
`RETRY: begin
if (discard_cnt == 15'b0 & ~ack_quiescence)
retry_ns = `DISCARD_CHK;
else
if (discard_cnt == 15'b0 & ack_quiescence)
retry_ns = `DISCARD_TO;
else
if ((cmd_start & ~cmd_start1 & pci_mem_rd & retry_addr_match &
~tar_xmt_fifo_empty & read_pack_done) | ack_quiescence) begin
//if (cmd_start & ~cmd_start1 & pci_mem_rd & retry_addr_match &
// ((~tar_xmt_fifo_empty & read_pack_done) | ack_quiescence)) begin
retry_ns = `RETRY_IDLE;
discard_cnt = discard_timer;
end
else begin
retry_ns = `RETRY;
if (discard_cnt != 15'b0)
discard_cnt = discard_count - 1'b1;
//else if (discard_cnt == 15'b0) begin
// retry_ns = `DISCARD_CHK;
//end
end
end
`DISCARD_CHK: begin
if (discard_ok)
retry_ns = `DISCARD_TO;
else
retry_ns = `DISCARD_CHK;
end
`DISCARD_TO: begin
discard_cnt = discard_timer;
retry_ns = `RETRY_IDLE;
end
default: begin
retry_ns = `RETRY_IDLE;
//synopsys translate_off
if (reset_l) $display("retry_sm: Error!");
//synopsys translate_on
end
endcase
end
force_retry_sm = {retry_ns, discard_cnt};
end
endfunction
reg [17:0] sm_output
;
always @(posedge pclk) begin
if (~reset_l)
sm_output[17:0] <= #1 {3'b0,discard_timer[14:0]};
else
sm_output[17:0] <= #1 force_retry_sm(retry_state,
reset_l, flush_stale_read, cmd_start, cmd_start1,
pci_mem_rd, pci_mem_wrt,
delayed_read, idle_cyc, write_fifos_empty,
tar_xmt_fifo_empty, retry_addr_match, read_pack_done,
ack_quiescence, discard_count, discard_timer, discard_ok);
end
assign retry_state[2:0] = sm_output[17:15];
assign discard_count[14:0] = sm_output[14:0];
wire save_addr = (retry_state==`SAVE_ADDR);
//wire force_pci_retry = (retry_state==`SAVE_ADDR) || (retry_state==`RETRY);
wire force_pci_retry = (retry_state!=`RETRY_IDLE);
wire discard_timeout = (retry_state==`DISCARD_TO);
endmodule
This page: |
Created: | Thu Aug 19 12:02:45 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/afxmaster/rtl/retry_sm.v
|