/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
![[Up: fp_rf fp_regfile]](v2html-up.gif)
module rf16x64_3r1w_2we
(doa63, doa62, doa61, doa60, doa59, doa58, doa57, doa56, doa55,
doa54, doa53, doa52, doa51, doa50, doa49, doa48, doa47, doa46, doa45, doa44, doa43,
doa42, doa41, doa40, doa39, doa38, doa37, doa36, doa35, doa34, doa33, doa32, doa31,
doa30, doa29, doa28, doa27, doa26, doa25, doa24, doa23, doa22, doa21, doa20, doa19,
doa18, doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7,
doa6, doa5, doa4, doa3, doa2, doa1, doa0, dob63, dob62, dob61, dob60, dob59, dob58,
dob57, dob56, dob55, dob54, dob53, dob52, dob51, dob50, dob49, dob48, dob47, dob46,
dob45, dob44, dob43, dob42, dob41, dob40, dob39, dob38, dob37, dob36, dob35, dob34,
dob33, dob32, dob31, dob30, dob29, dob28, dob27, dob26, dob25, dob24, dob23, dob22,
dob21, dob20, dob19, dob18, dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10,
dob9, dob8, dob7, dob6, dob5, dob4, dob3, dob2, dob1, dob0, doc63, doc62, doc61,
doc60, doc59, doc58, doc57, doc56, doc55, doc54, doc53, doc52, doc51, doc50, doc49,
doc48, doc47, doc46, doc45, doc44, doc43, doc42, doc41, doc40, doc39, doc38, doc37,
doc36, doc35, doc34, doc33, doc32, doc31, doc30, doc29, doc28, doc27, doc26, doc25,
doc24, doc23, doc22, doc21, doc20, doc19, doc18, doc17, doc16, doc15, doc14, doc13,
doc12, doc11, doc10, doc9, doc8, doc7, doc6, doc5, doc4, doc3, doc2, doc1, doc0,
did63, did62, did61, did60, did59, did58, did57, did56, did55, did54, did53, did52,
did51, did50, did49, did48, did47, did46, did45, did44, did43, did42, did41, did40,
did39, did38, did37, did36, did35, did34, did33, did32, did31, did30, did29, did28,
did27, did26, did25, did24, did23, did22, did21, did20, did19, did18, did17, did16,
did15, did14, did13, did12, did11, did10, did9, did8, did7, did6, did5, did4, did3,
did2, did1, did0, aadr3, aadr2, aadr1, aadr0, badr3, badr2, badr1, badr0,
cadr3, cadr2, cadr1, cadr0, dadr3, dadr2, dadr1, dadr0, wed1, wed0, cpd);
// cpa, cpb, cpc,
output doa63;
output doa62;
output doa61;
output doa60;
output doa59;
output doa58;
output doa57;
output doa56;
output doa55;
output doa54;
output doa53;
output doa52;
output doa51;
output doa50;
output doa49;
output doa48;
output doa47;
output doa46;
output doa45;
output doa44;
output doa43;
output doa42;
output doa41;
output doa40;
output doa39;
output doa38;
output doa37;
output doa36;
output doa35;
output doa34;
output doa33;
output doa32;
output doa31;
output doa30;
output doa29;
output doa28;
output doa27;
output doa26;
output doa25;
output doa24;
output doa23;
output doa22;
output doa21;
output doa20;
output doa19;
output doa18;
output doa17;
output doa16;
output doa15;
output doa14;
output doa13;
output doa12;
output doa11;
output doa10;
output doa9;
output doa8;
output doa7;
output doa6;
output doa5;
output doa4;
output doa3;
output doa2;
output doa1;
output doa0;
output dob63;
output dob62;
output dob61;
output dob60;
output dob59;
output dob58;
output dob57;
output dob56;
output dob55;
output dob54;
output dob53;
output dob52;
output dob51;
output dob50;
output dob49;
output dob48;
output dob47;
output dob46;
output dob45;
output dob44;
output dob43;
output dob42;
output dob41;
output dob40;
output dob39;
output dob38;
output dob37;
output dob36;
output dob35;
output dob34;
output dob33;
output dob32;
output dob31;
output dob30;
output dob29;
output dob28;
output dob27;
output dob26;
output dob25;
output dob24;
output dob23;
output dob22;
output dob21;
output dob20;
output dob19;
output dob18;
output dob17;
output dob16;
output dob15;
output dob14;
output dob13;
output dob12;
output dob11;
output dob10;
output dob9;
output dob8;
output dob7;
output dob6;
output dob5;
output dob4;
output dob3;
output dob2;
output dob1;
output dob0;
output doc63;
output doc62;
output doc61;
output doc60;
output doc59;
output doc58;
output doc57;
output doc56;
output doc55;
output doc54;
output doc53;
output doc52;
output doc51;
output doc50;
output doc49;
output doc48;
output doc47;
output doc46;
output doc45;
output doc44;
output doc43;
output doc42;
output doc41;
output doc40;
output doc39;
output doc38;
output doc37;
output doc36;
output doc35;
output doc34;
output doc33;
output doc32;
output doc31;
output doc30;
output doc29;
output doc28;
output doc27;
output doc26;
output doc25;
output doc24;
output doc23;
output doc22;
output doc21;
output doc20;
output doc19;
output doc18;
output doc17;
output doc16;
output doc15;
output doc14;
output doc13;
output doc12;
output doc11;
output doc10;
output doc9;
output doc8;
output doc7;
output doc6;
output doc5;
output doc4;
output doc3;
output doc2;
output doc1;
output doc0;
input did63;
input did62;
input did61;
input did60;
input did59;
input did58;
input did57;
input did56;
input did55;
input did54;
input did53;
input did52;
input did51;
input did50;
input did49;
input did48;
input did47;
input did46;
input did45;
input did44;
input did43;
input did42;
input did41;
input did40;
input did39;
input did38;
input did37;
input did36;
input did35;
input did34;
input did33;
input did32;
input did31;
input did30;
input did29;
input did28;
input did27;
input did26;
input did25;
input did24;
input did23;
input did22;
input did21;
input did20;
input did19;
input did18;
input did17;
input did16;
input did15;
input did14;
input did13;
input did12;
input did11;
input did10;
input did9;
input did8;
input did7;
input did6;
input did5;
input did4;
input did3;
input did2;
input did1;
input did0;
input aadr3;
input aadr2;
input aadr1;
input aadr0;
// input cpa;
input badr3;
input badr2;
input badr1;
input badr0;
// input cpb;
input cadr3;
input cadr2;
input cadr1;
input cadr0;
// input cpc;
input dadr3;
input dadr2;
input dadr1;
input dadr0;
input wed1;
input wed0;
input cpd;
/* moved further down by kumar
//synopsys translate_off
*/
// reconnect ss_clock internally from cpa read clock strobe.
//-------------------------------------------------------------
wire ss_clock = cpd ;
wire #1 delay_clock = ss_clock ;
// delayed clock is used to improve simulation
// efficiency; since most of the inputs will
// change at #1 after the clock, delaying the
// clock internally will cause only 1 evalua-
// tion per clock cycle
// data register input to Ram Core
wire [63:0] inreg_din ;
wire [1:0] gated_we ;
assign gated_we[0] = wed0 ;
assign gated_we[1] = wed1 ;
//event update; // triggered when a register is written
wire [3:0] inreg_wa; // write address
wire [3:0] inreg_ra1; // read address 1
wire [3:0] inreg_ra2; // read address 2
wire [3:0] inreg_ra3; // read address 3
assign inreg_wa[3] = dadr3;
assign inreg_wa[2] = dadr2;
assign inreg_wa[1] = dadr1;
assign inreg_wa[0] = dadr0;
assign inreg_ra1[3] = aadr3;
assign inreg_ra1[2] = aadr2;
assign inreg_ra1[1] = aadr1;
assign inreg_ra1[0] = aadr0;
assign inreg_ra2[3] = badr3;
assign inreg_ra2[2] = badr2;
assign inreg_ra2[1] = badr1;
assign inreg_ra2[0] = badr0;
assign inreg_ra3[3] = cadr3;
assign inreg_ra3[2] = cadr2;
assign inreg_ra3[1] = cadr1;
assign inreg_ra3[0] = cadr0;
//=====================================================================
// instantiate hardware ram
reg [31:0] rf_even[15:0], rf_odd[15:0] ;
// RF write model -- trash reg file if write enable ever goes unknown
//---------------------------------------------------------------------------
always @ (posedge delay_clock) begin
if (gated_we[1] == 1'b1) begin // write the ram
rf_even[inreg_wa] = inreg_din[63:32];
end
//synopsys translate_off
else if (gated_we[1] === 1'bx) begin // trash the ram
rf_even[inreg_wa] = 32'hx;
if(~`SS_SCOPE.reset && ( $time > 15 ))
$display("*** X on fp_we[1] - FPU register file trashed");
end
//synopsys translate_on
if (gated_we[0] == 1'b1) begin // write the ram
rf_odd[inreg_wa] = inreg_din[31:0];
end
//synopsys translate_off
else if (gated_we[0] === 1'bx) begin // trash the ram
rf_odd[inreg_wa] = 32'hx;
if(~`SS_SCOPE.reset && ( $time > 15 ))
$display("*** X on fp_we[0] - FPU register file trashed");
end
//synopsys translate_on
end
// RF read model -- if trying to read from a register that is
// being written to, and bypass is inactive,
// want it to read as x's only while the write
// enable is active.
//---------------------------------------------------------------------------
wire [63:0] rd1, rd2, rd3;
// read port 1
//--------------------------------------
assign rd1[31:0] =
((inreg_ra1 == inreg_wa) && (gated_we[0] != 1'b0)) ?
32'hx : rf_odd[inreg_ra1] ;
assign rd1[63:32] =
((inreg_ra1 == inreg_wa) && (gated_we[1] != 1'b0)) ?
32'hx : rf_even[inreg_ra1] ;
// read port 2
//--------------------------------------
assign rd2[31:0] =
((inreg_ra2 == inreg_wa) && (gated_we[0] != 1'b0)) ?
32'hx : rf_odd[inreg_ra2] ;
assign rd2[63:32] =
((inreg_ra2 == inreg_wa) && (gated_we[1] != 1'b0)) ?
32'hx : rf_even[inreg_ra2] ;
// read port 3
//--------------------------------------
assign rd3[31:0] =
((inreg_ra3 == inreg_wa) && (gated_we[0] != 1'b0)) ?
32'hx : rf_odd[inreg_ra3] ;
assign rd3[63:32] =
((inreg_ra3 == inreg_wa) && (gated_we[1] != 1'b0)) ?
32'hx : rf_even[inreg_ra3] ;
//=====================================================================
// WRITE DATA PORT
assign inreg_din[63] = did63;
assign inreg_din[62] = did62;
assign inreg_din[61] = did61;
assign inreg_din[60] = did60;
assign inreg_din[59] = did59;
assign inreg_din[58] = did58;
assign inreg_din[57] = did57;
assign inreg_din[56] = did56;
assign inreg_din[55] = did55;
assign inreg_din[54] = did54;
assign inreg_din[53] = did53;
assign inreg_din[52] = did52;
assign inreg_din[51] = did51;
assign inreg_din[50] = did50;
assign inreg_din[49] = did49;
assign inreg_din[48] = did48;
assign inreg_din[47] = did47;
assign inreg_din[46] = did46;
assign inreg_din[45] = did45;
assign inreg_din[44] = did44;
assign inreg_din[43] = did43;
assign inreg_din[42] = did42;
assign inreg_din[41] = did41;
assign inreg_din[40] = did40;
assign inreg_din[39] = did39;
assign inreg_din[38] = did38;
assign inreg_din[37] = did37;
assign inreg_din[36] = did36;
assign inreg_din[35] = did35;
assign inreg_din[34] = did34;
assign inreg_din[33] = did33;
assign inreg_din[32] = did32;
assign inreg_din[31] = did31;
assign inreg_din[30] = did30;
assign inreg_din[29] = did29;
assign inreg_din[28] = did28;
assign inreg_din[27] = did27;
assign inreg_din[26] = did26;
assign inreg_din[25] = did25;
assign inreg_din[24] = did24;
assign inreg_din[23] = did23;
assign inreg_din[22] = did22;
assign inreg_din[21] = did21;
assign inreg_din[20] = did20;
assign inreg_din[19] = did19;
assign inreg_din[18] = did18;
assign inreg_din[17] = did17;
assign inreg_din[16] = did16;
assign inreg_din[15] = did15;
assign inreg_din[14] = did14;
assign inreg_din[13] = did13;
assign inreg_din[12] = did12;
assign inreg_din[11] = did11;
assign inreg_din[10] = did10;
assign inreg_din[9] = did9;
assign inreg_din[8] = did8;
assign inreg_din[7] = did7;
assign inreg_din[6] = did6;
assign inreg_din[5] = did5;
assign inreg_din[4] = did4;
assign inreg_din[3] = did3;
assign inreg_din[2] = did2;
assign inreg_din[1] = did1;
assign inreg_din[0] = did0;
//--------------------------------------------------
// READ DATA PORT A
assign doa63 = rd1[63];
assign doa62 = rd1[62];
assign doa61 = rd1[61];
assign doa60 = rd1[60];
assign doa59 = rd1[59];
assign doa58 = rd1[58];
assign doa57 = rd1[57];
assign doa56 = rd1[56];
assign doa55 = rd1[55];
assign doa54 = rd1[54];
assign doa53 = rd1[53];
assign doa52 = rd1[52];
assign doa51 = rd1[51];
assign doa50 = rd1[50];
assign doa49 = rd1[49];
assign doa48 = rd1[48];
assign doa47 = rd1[47];
assign doa46 = rd1[46];
assign doa45 = rd1[45];
assign doa44 = rd1[44];
assign doa43 = rd1[43];
assign doa42 = rd1[42];
assign doa41 = rd1[41];
assign doa40 = rd1[40];
assign doa39 = rd1[39];
assign doa38 = rd1[38];
assign doa37 = rd1[37];
assign doa36 = rd1[36];
assign doa35 = rd1[35];
assign doa34 = rd1[34];
assign doa33 = rd1[33];
assign doa32 = rd1[32];
assign doa31 = rd1[31];
assign doa30 = rd1[30];
assign doa29 = rd1[29];
assign doa28 = rd1[28];
assign doa27 = rd1[27];
assign doa26 = rd1[26];
assign doa25 = rd1[25];
assign doa24 = rd1[24];
assign doa23 = rd1[23];
assign doa22 = rd1[22];
assign doa21 = rd1[21];
assign doa20 = rd1[20];
assign doa19 = rd1[19];
assign doa18 = rd1[18];
assign doa17 = rd1[17];
assign doa16 = rd1[16];
assign doa15 = rd1[15];
assign doa14 = rd1[14];
assign doa13 = rd1[13];
assign doa12 = rd1[12];
assign doa11 = rd1[11];
assign doa10 = rd1[10];
assign doa9 = rd1[9];
assign doa8 = rd1[8];
assign doa7 = rd1[7];
assign doa6 = rd1[6];
assign doa5 = rd1[5];
assign doa4 = rd1[4];
assign doa3 = rd1[3];
assign doa2 = rd1[2];
assign doa1 = rd1[1];
assign doa0 = rd1[0];
// READ DATA PORT B
assign dob63 = rd2[63];
assign dob62 = rd2[62];
assign dob61 = rd2[61];
assign dob60 = rd2[60];
assign dob59 = rd2[59];
assign dob58 = rd2[58];
assign dob57 = rd2[57];
assign dob56 = rd2[56];
assign dob55 = rd2[55];
assign dob54 = rd2[54];
assign dob53 = rd2[53];
assign dob52 = rd2[52];
assign dob51 = rd2[51];
assign dob50 = rd2[50];
assign dob49 = rd2[49];
assign dob48 = rd2[48];
assign dob47 = rd2[47];
assign dob46 = rd2[46];
assign dob45 = rd2[45];
assign dob44 = rd2[44];
assign dob43 = rd2[43];
assign dob42 = rd2[42];
assign dob41 = rd2[41];
assign dob40 = rd2[40];
assign dob39 = rd2[39];
assign dob38 = rd2[38];
assign dob37 = rd2[37];
assign dob36 = rd2[36];
assign dob35 = rd2[35];
assign dob34 = rd2[34];
assign dob33 = rd2[33];
assign dob32 = rd2[32];
assign dob31 = rd2[31];
assign dob30 = rd2[30];
assign dob29 = rd2[29];
assign dob28 = rd2[28];
assign dob27 = rd2[27];
assign dob26 = rd2[26];
assign dob25 = rd2[25];
assign dob24 = rd2[24];
assign dob23 = rd2[23];
assign dob22 = rd2[22];
assign dob21 = rd2[21];
assign dob20 = rd2[20];
assign dob19 = rd2[19];
assign dob18 = rd2[18];
assign dob17 = rd2[17];
assign dob16 = rd2[16];
assign dob15 = rd2[15];
assign dob14 = rd2[14];
assign dob13 = rd2[13];
assign dob12 = rd2[12];
assign dob11 = rd2[11];
assign dob10 = rd2[10];
assign dob9 = rd2[9];
assign dob8 = rd2[8];
assign dob7 = rd2[7];
assign dob6 = rd2[6];
assign dob5 = rd2[5];
assign dob4 = rd2[4];
assign dob3 = rd2[3];
assign dob2 = rd2[2];
assign dob1 = rd2[1];
assign dob0 = rd2[0];
// READ DATA PORT C
assign doc63 = rd3[63];
assign doc62 = rd3[62];
assign doc61 = rd3[61];
assign doc60 = rd3[60];
assign doc59 = rd3[59];
assign doc58 = rd3[58];
assign doc57 = rd3[57];
assign doc56 = rd3[56];
assign doc55 = rd3[55];
assign doc54 = rd3[54];
assign doc53 = rd3[53];
assign doc52 = rd3[52];
assign doc51 = rd3[51];
assign doc50 = rd3[50];
assign doc49 = rd3[49];
assign doc48 = rd3[48];
assign doc47 = rd3[47];
assign doc46 = rd3[46];
assign doc45 = rd3[45];
assign doc44 = rd3[44];
assign doc43 = rd3[43];
assign doc42 = rd3[42];
assign doc41 = rd3[41];
assign doc40 = rd3[40];
assign doc39 = rd3[39];
assign doc38 = rd3[38];
assign doc37 = rd3[37];
assign doc36 = rd3[36];
assign doc35 = rd3[35];
assign doc34 = rd3[34];
assign doc33 = rd3[33];
assign doc32 = rd3[32];
assign doc31 = rd3[31];
assign doc30 = rd3[30];
assign doc29 = rd3[29];
assign doc28 = rd3[28];
assign doc27 = rd3[27];
assign doc26 = rd3[26];
assign doc25 = rd3[25];
assign doc24 = rd3[24];
assign doc23 = rd3[23];
assign doc22 = rd3[22];
assign doc21 = rd3[21];
assign doc20 = rd3[20];
assign doc19 = rd3[19];
assign doc18 = rd3[18];
assign doc17 = rd3[17];
assign doc16 = rd3[16];
assign doc15 = rd3[15];
assign doc14 = rd3[14];
assign doc13 = rd3[13];
assign doc12 = rd3[12];
assign doc11 = rd3[11];
assign doc10 = rd3[10];
assign doc9 = rd3[9];
assign doc8 = rd3[8];
assign doc7 = rd3[7];
assign doc6 = rd3[6];
assign doc5 = rd3[5];
assign doc4 = rd3[4];
assign doc3 = rd3[3];
assign doc2 = rd3[2];
assign doc1 = rd3[1];
assign doc0 = rd3[0];
//synopsys translate_off
// Verification Tasks
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// reg file dump task
// FP Register logging at the completion of a run ("fdump" command).
//----------------------------------------------------------------------------
task fdump ;
reg [31:0] mcd ; // multi-channel descriptor
integer i ;
reg [31:0] value_h, value_l ;
begin
mcd = $fopen({Mclocks.working_dir,"/fdump.v"});
if ( mcd) begin
// Display FSR first..
$fdisplay( mcd, " 0x%x",fpusas_sig.fsr);
// .. followed by the 32 FP Registers in ascending order.
for (i=0; i<16; i=i+1) begin
value_h = rf_even[i] ;
value_l = rf_odd[i] ;
$fdisplay( mcd, " 0x%x",value_h) ;
$fdisplay( mcd, " 0x%x",value_l);
end
$fclose( mcd) ;
end
else
$display( "FPU: unable to open 'fdump.v'") ;
end // fdump task
endtask
// vfront F command dump
//----------------------------------------------------------------------------
task disp_frf ;
reg [31:0] value_h, value_l ;
integer i;
begin
// display the F registers as 16 even odd pairs
$display("");
$display(" F REG even odd");
$display(" ----- ---------- ----------");
for (i=0; i<16; i=i+1) begin
value_h = rf_even[i] ;
value_l = rf_odd[i] ;
$display("%d 0x%x 0x%x",i*2,value_h,value_l) ;
end
$display("");
end
endtask
// function to initialize all the FP regs to a given value
//----------------------------------------------------------------------------
task init_frf ;
input [31:0] value ;
integer i ;
for (i=0; i<16; i=i+1) begin
rf_even[i] = value ;
rf_odd[i] = value ;
end
endtask
//synopsys translate_on
endmodule
| This page: |
Created: | Thu Aug 19 12:02:41 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_rf/rtl/rf16x64.v
|