/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
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/******************************************************************************/
/* ******************************************************************
@(#)fp_rf.v 1.9 4/15/93
Verilog model of the FPU Register File (16x64-bit, 3 read ports, 1 write
port, and 2 write enables) which conforms to the specifi-
cation. There are 2 write enable signals: fp_we[1] controls writes to
the even word; fp_we[0] controls writes to the odd word.
****************************************************************** */
![[Up: fpufpc fprf]](v2html-up.gif)
module fp_rf
( ss_clock, ss_scan_mode, fp_scan_in, hold_din,
fp_hold_ra3, fp_we, fp_algn1, fp_algn2,
fp_byp1, fp_byp2, fp_byp3,
fp_wa, fp_ra1, fp_ra2, fp_ra3,
fp_din, fp_dout1, fp_dout2, fp_dout3,
fp_scan_out );
input ss_clock, ss_scan_mode, fp_scan_in ;
input [ 1:0] hold_din ;
input fp_hold_ra3 ;
input [ 1:0] fp_we ;
input [ 1:0] fp_algn1, fp_algn2 ;
input [ 5:0] fp_byp1, fp_byp2, fp_byp3 ;
input [ 3:0] fp_wa, fp_ra1, fp_ra2, fp_ra3 ;
input [63:0] fp_din ;
output [63:0] fp_dout1, fp_dout2, fp_dout3 ;
output fp_scan_out ;
// delayed clock is used to improve simulation
// efficiency; since most of the inputs will
// change at #1 after the clock, delaying the
// clock internally will cause only 1 evalua-
// tion per clock cycle
wire #1 delay_clock = ss_clock ;
wire [63:0] rd1 ; // Ram Core: Read Data 1 output
wire [63:0] rd2 ; // Ram Core: Read Data 2 output
wire [63:0] rd3 ; // Ram Core: Read Data 3 output
// instantiate hardware registers
reg [ 1:0] inreg_we ; // write enable
reg [ 3:0] inreg_wa, inreg_ra1, inreg_ra2, inreg_ra3 ; // address registers
reg [63:0] inreg_din ; // data register
reg [63:0] do1, do2, do3 ; // instantiate dummy simulation registers
assign fp_dout1 = do1 ;
assign fp_dout2 = do2 ;
assign fp_dout3 = do3 ;
// event update; // triggered when a register is written
// update internal registers immediately after clock;
// must use the setup value of hold_din
// scan order = scan_in->we[1:0]->wa[0:3]->ra1[0:3]->
// ra2[0:3]->ra3[0:3]->din[0:63]->scan_out
always @ (posedge ss_clock) begin
if (hold_din[1] == 1'b0) begin // load data into reg.
inreg_din[63:32] = fp_din[63:32] ;
end
if (hold_din[0] == 1'b0) begin // load data into reg.
inreg_din[31:0] = fp_din[31:0] ;
end
if (fp_hold_ra3 == 1'b0) begin // load data into reg.
inreg_ra3[3:0] = fp_ra3[3:0] ;
end
begin
inreg_ra2[3:0] = fp_ra2[3:0] ; // load data into regs
inreg_ra1[3:0] = fp_ra1[3:0] ;
inreg_wa[3:0] = fp_wa[3:0] ;
inreg_we[1:0] = fp_we[1:0] ;
end
end
//----------------------------------------------------------------------------
rf16x64_3r1w_2we fp_regfile (
.doa63( rd1[63] ),
.doa62( rd1[62] ),
.doa61( rd1[61] ),
.doa60( rd1[60] ),
.doa59( rd1[59] ),
.doa58( rd1[58] ),
.doa57( rd1[57] ),
.doa56( rd1[56] ),
.doa55( rd1[55] ),
.doa54( rd1[54] ),
.doa53( rd1[53] ),
.doa52( rd1[52] ),
.doa51( rd1[51] ),
.doa50( rd1[50] ),
.doa49( rd1[49] ),
.doa48( rd1[48] ),
.doa47( rd1[47] ),
.doa46( rd1[46] ),
.doa45( rd1[45] ),
.doa44( rd1[44] ),
.doa43( rd1[43] ),
.doa42( rd1[42] ),
.doa41( rd1[41] ),
.doa40( rd1[40] ),
.doa39( rd1[39] ),
.doa38( rd1[38] ),
.doa37( rd1[37] ),
.doa36( rd1[36] ),
.doa35( rd1[35] ),
.doa34( rd1[34] ),
.doa33( rd1[33] ),
.doa32( rd1[32] ),
.doa31( rd1[31] ),
.doa30( rd1[30] ),
.doa29( rd1[29] ),
.doa28( rd1[28] ),
.doa27( rd1[27] ),
.doa26( rd1[26] ),
.doa25( rd1[25] ),
.doa24( rd1[24] ),
.doa23( rd1[23] ),
.doa22( rd1[22] ),
.doa21( rd1[21] ),
.doa20( rd1[20] ),
.doa19( rd1[19] ),
.doa18( rd1[18] ),
.doa17( rd1[17] ),
.doa16( rd1[16] ),
.doa15( rd1[15] ),
.doa14( rd1[14] ),
.doa13( rd1[13] ),
.doa12( rd1[12] ),
.doa11( rd1[11] ),
.doa10( rd1[10] ),
.doa9( rd1[9] ),
.doa8( rd1[8] ),
.doa7( rd1[7] ),
.doa6( rd1[6] ),
.doa5( rd1[5] ),
.doa4( rd1[4] ),
.doa3( rd1[3] ),
.doa2( rd1[2] ),
.doa1( rd1[1] ),
.doa0( rd1[0] ),
.dob63( rd2[63] ),
.dob62( rd2[62] ),
.dob61( rd2[61] ),
.dob60( rd2[60] ),
.dob59( rd2[59] ),
.dob58( rd2[58] ),
.dob57( rd2[57] ),
.dob56( rd2[56] ),
.dob55( rd2[55] ),
.dob54( rd2[54] ),
.dob53( rd2[53] ),
.dob52( rd2[52] ),
.dob51( rd2[51] ),
.dob50( rd2[50] ),
.dob49( rd2[49] ),
.dob48( rd2[48] ),
.dob47( rd2[47] ),
.dob46( rd2[46] ),
.dob45( rd2[45] ),
.dob44( rd2[44] ),
.dob43( rd2[43] ),
.dob42( rd2[42] ),
.dob41( rd2[41] ),
.dob40( rd2[40] ),
.dob39( rd2[39] ),
.dob38( rd2[38] ),
.dob37( rd2[37] ),
.dob36( rd2[36] ),
.dob35( rd2[35] ),
.dob34( rd2[34] ),
.dob33( rd2[33] ),
.dob32( rd2[32] ),
.dob31( rd2[31] ),
.dob30( rd2[30] ),
.dob29( rd2[29] ),
.dob28( rd2[28] ),
.dob27( rd2[27] ),
.dob26( rd2[26] ),
.dob25( rd2[25] ),
.dob24( rd2[24] ),
.dob23( rd2[23] ),
.dob22( rd2[22] ),
.dob21( rd2[21] ),
.dob20( rd2[20] ),
.dob19( rd2[19] ),
.dob18( rd2[18] ),
.dob17( rd2[17] ),
.dob16( rd2[16] ),
.dob15( rd2[15] ),
.dob14( rd2[14] ),
.dob13( rd2[13] ),
.dob12( rd2[12] ),
.dob11( rd2[11] ),
.dob10( rd2[10] ),
.dob9( rd2[9] ),
.dob8( rd2[8] ),
.dob7( rd2[7] ),
.dob6( rd2[6] ),
.dob5( rd2[5] ),
.dob4( rd2[4] ),
.dob3( rd2[3] ),
.dob2( rd2[2] ),
.dob1( rd2[1] ),
.dob0( rd2[0] ),
.doc63( rd3[63] ),
.doc62( rd3[62] ),
.doc61( rd3[61] ),
.doc60( rd3[60] ),
.doc59( rd3[59] ),
.doc58( rd3[58] ),
.doc57( rd3[57] ),
.doc56( rd3[56] ),
.doc55( rd3[55] ),
.doc54( rd3[54] ),
.doc53( rd3[53] ),
.doc52( rd3[52] ),
.doc51( rd3[51] ),
.doc50( rd3[50] ),
.doc49( rd3[49] ),
.doc48( rd3[48] ),
.doc47( rd3[47] ),
.doc46( rd3[46] ),
.doc45( rd3[45] ),
.doc44( rd3[44] ),
.doc43( rd3[43] ),
.doc42( rd3[42] ),
.doc41( rd3[41] ),
.doc40( rd3[40] ),
.doc39( rd3[39] ),
.doc38( rd3[38] ),
.doc37( rd3[37] ),
.doc36( rd3[36] ),
.doc35( rd3[35] ),
.doc34( rd3[34] ),
.doc33( rd3[33] ),
.doc32( rd3[32] ),
.doc31( rd3[31] ),
.doc30( rd3[30] ),
.doc29( rd3[29] ),
.doc28( rd3[28] ),
.doc27( rd3[27] ),
.doc26( rd3[26] ),
.doc25( rd3[25] ),
.doc24( rd3[24] ),
.doc23( rd3[23] ),
.doc22( rd3[22] ),
.doc21( rd3[21] ),
.doc20( rd3[20] ),
.doc19( rd3[19] ),
.doc18( rd3[18] ),
.doc17( rd3[17] ),
.doc16( rd3[16] ),
.doc15( rd3[15] ),
.doc14( rd3[14] ),
.doc13( rd3[13] ),
.doc12( rd3[12] ),
.doc11( rd3[11] ),
.doc10( rd3[10] ),
.doc9( rd3[9] ),
.doc8( rd3[8] ),
.doc7( rd3[7] ),
.doc6( rd3[6] ),
.doc5( rd3[5] ),
.doc4( rd3[4] ),
.doc3( rd3[3] ),
.doc2( rd3[2] ),
.doc1( rd3[1] ),
.doc0( rd3[0] ),
.did63(inreg_din[63] ),
.did62(inreg_din[62] ),
.did61(inreg_din[61] ),
.did60(inreg_din[60] ),
.did59(inreg_din[59] ),
.did58(inreg_din[58] ),
.did57(inreg_din[57] ),
.did56(inreg_din[56] ),
.did55(inreg_din[55] ),
.did54(inreg_din[54] ),
.did53(inreg_din[53] ),
.did52(inreg_din[52] ),
.did51(inreg_din[51] ),
.did50(inreg_din[50] ),
.did49(inreg_din[49] ),
.did48(inreg_din[48] ),
.did47(inreg_din[47] ),
.did46(inreg_din[46] ),
.did45(inreg_din[45] ),
.did44(inreg_din[44] ),
.did43(inreg_din[43] ),
.did42(inreg_din[42] ),
.did41(inreg_din[41] ),
.did40(inreg_din[40] ),
.did39(inreg_din[39] ),
.did38(inreg_din[38] ),
.did37(inreg_din[37] ),
.did36(inreg_din[36] ),
.did35(inreg_din[35] ),
.did34(inreg_din[34] ),
.did33(inreg_din[33] ),
.did32(inreg_din[32] ),
.did31(inreg_din[31] ),
.did30(inreg_din[30] ),
.did29(inreg_din[29] ),
.did28(inreg_din[28] ),
.did27(inreg_din[27] ),
.did26(inreg_din[26] ),
.did25(inreg_din[25] ),
.did24(inreg_din[24] ),
.did23(inreg_din[23] ),
.did22(inreg_din[22] ),
.did21(inreg_din[21] ),
.did20(inreg_din[20] ),
.did19(inreg_din[19] ),
.did18(inreg_din[18] ),
.did17(inreg_din[17] ),
.did16(inreg_din[16] ),
.did15(inreg_din[15] ),
.did14(inreg_din[14] ),
.did13(inreg_din[13] ),
.did12(inreg_din[12] ),
.did11(inreg_din[11] ),
.did10(inreg_din[10] ),
.did9(inreg_din[9] ),
.did8(inreg_din[8] ),
.did7(inreg_din[7] ),
.did6(inreg_din[6] ),
.did5(inreg_din[5] ),
.did4(inreg_din[4] ),
.did3(inreg_din[3] ),
.did2(inreg_din[2] ),
.did1(inreg_din[1] ),
.did0(inreg_din[0] ),
.aadr3(inreg_ra1[3] ),
.aadr2(inreg_ra1[2] ),
.aadr1(inreg_ra1[1] ),
.aadr0(inreg_ra1[0] ),
// .cpa(ss_clock),
.badr3(inreg_ra2[3] ),
.badr2(inreg_ra2[2] ),
.badr1(inreg_ra2[1] ),
.badr0(inreg_ra2[0] ),
// .cpb(ss_clock),
.cadr3(inreg_ra3[3] ),
.cadr2(inreg_ra3[2] ),
.cadr1(inreg_ra3[1] ),
.cadr0(inreg_ra3[0] ),
// .cpc(ss_clock),
.dadr3( inreg_wa[3] ),
.dadr2( inreg_wa[2] ),
.dadr1( inreg_wa[1] ),
.dadr0( inreg_wa[0] ),
.wed1( inreg_we[1] ),
.wed0( inreg_we[0] ),
.cpd( ss_clock )
);
//----------------------------------------------------------------------------
always @ (rd1 or rd2 or rd3 or fp_din or fp_byp1 or
fp_algn1 or fp_byp2 or fp_algn2 or fp_byp3) begin
// ******************************************************************
// read port 1
case (fp_byp1[2:0]) // low-order bits
3'b001: begin
do1[31:0] = rd1[31:0]; // Ram Core Read Output 1
end
3'b010: do1[31:0] = fp_din[31:0] ; // bypass 1
3'b100: do1[31:0] = inreg_din[31:0] ; // bypass 2
default do1[31:0] = 32'hx;
endcase
case (fp_byp1[5:3]) // high-order bits
3'b001: begin
do1[63:32] = rd1[63:32]; // Ram Core Read Output 1
end
3'b010: do1[63:32] = fp_din[63:32] ; // bypass 1
3'b100: do1[63:32] = inreg_din[63:32] ; // bypass 2
default do1[63:32] = 32'hx;
endcase
case (fp_algn1[1:0]) // alignment
2'b01: ; // double (do nothing)
2'b10: do1[63:32] = do1[31:0] ; // single
default do1[63:32] = 32'hx ;
endcase
// ******************************************************************
// read port 2
case (fp_byp2[2:0]) // low-order bits
3'b001: begin
do2[31:0] = rd2[31:0]; // Ram Core Read Output 2
end
3'b010: do2[31:0] = fp_din[31:0] ; // bypass 1
3'b100: do2[31:0] = inreg_din[31:0] ; // bypass 2
default do2[31:0] = 32'hx;
endcase
case (fp_byp2[5:3]) // high-order bits
3'b001: begin
do2[63:32] = rd2[63:32]; // Ram Core Read Output 2
end
3'b010: do2[63:32] = fp_din[63:32] ; // bypass 1
3'b100: do2[63:32] = inreg_din[63:32] ; // bypass 2
default do2[63:32] = 32'hx;
endcase
case (fp_algn2[1:0]) // alignment
2'b01: ; // double (do nothing)
2'b10: do2[63:32] = do2[31:0] ; // single
default do2[63:32] = 32'hx ;
endcase
// ******************************************************************
// read port 3
case (fp_byp3[2:0]) // low-order bits
3'b001: begin
do3[31:0] = rd3[31:0]; // Ram Core Read Output 3
end
3'b010: do3[31:0] = fp_din[31:0] ; // bypass 1
3'b100: do3[31:0] = inreg_din[31:0] ; // bypass 2
default do3[31:0] = 32'hx;
endcase
case (fp_byp3[5:3]) // high-order bits
3'b001: begin
do3[63:32] = rd3[63:32]; // Ram Core Read Output 3
end
3'b010: do3[63:32] = fp_din[63:32] ; // bypass 1
3'b100: do3[63:32] = inreg_din[63:32] ; // bypass 2
default do3[63:32] = 32'hx;
endcase
end
endmodule
| This page: |
Created: | Thu Aug 19 12:00:16 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_rf/rtl/fp_rf.v
|