/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
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/******************************************************************************/ 

module HP136X32 (DOA31,DOA30,DOA29,DOA28,DOA27,DOA26,DOA25,DOA24,DOA23,DOA22,DOA21,DOA20,DOA19,DOA18,DOA17,DOA16,DOA15,DOA14,DOA13,DOA12,DOA11,DOA10,DOA9,DOA8,DOA7,DOA6,DOA5,DOA4,DOA3,DOA2,DOA1,DOA0,
DOB31,DOB30,DOB29,DOB28,DOB27,DOB26,DOB25,DOB24,DOB23,DOB22,DOB21,DOB20,DOB19,DOB18,DOB17,DOB16,DOB15,DOB14,DOB13,DOB12,DOB11,DOB10,DOB9,DOB8,DOB7,DOB6,DOB5,DOB4,DOB3,DOB2,DOB1,DOB0,
DOC31,DOC30,DOC29,DOC28,DOC27,DOC26,DOC25,DOC24,DOC23,DOC22,DOC21,DOC20,DOC19,DOC18,DOC17,DOC16,DOC15,DOC14,DOC13,DOC12,DOC11,DOC10,DOC9,DOC8,DOC7,DOC6,DOC5,DOC4,DOC3,DOC2,DOC1,DOC0,
WED,
OEA,
OEB,
OEC,
DID31,DID30,DID29,DID28,DID27,DID26,DID25,DID24,DID23,DID22,DID21,DID20,DID19,DID18,DID17,DID16,DID15,DID14,DID13,DID12,DID11,DID10,DID9,DID8,DID7,DID6,DID5,DID4,DID3,DID2,DID1,DID0,
AADR7,AADR6,AADR5,AADR4,AADR3,AADR2,AADR1,AADR0,
BADR7,BADR6,BADR5,BADR4,BADR3,BADR2,BADR1,BADR0,
CADR7,CADR6,CADR5,CADR4,CADR3,CADR2,CADR1,CADR0,
DADR7,DADR6,DADR5,DADR4,DADR3,DADR2,DADR1,DADR0);

input WED,
OEA,
OEB,
OEC,
DID31,DID30,DID29,DID28,DID27,DID26,DID25,DID24,DID23,DID22,DID21,DID20,DID19,DID18,DID17,DID16,DID15,DID14,DID13,DID12,DID11,DID10,DID9,DID8,DID7,DID6,DID5,DID4,DID3,DID2,DID1,DID0,
AADR7,AADR6,AADR5,AADR4,AADR3,AADR2,AADR1,AADR0,
BADR7,BADR6,BADR5,BADR4,BADR3,BADR2,BADR1,BADR0,
CADR7,CADR6,CADR5,CADR4,CADR3,CADR2,CADR1,CADR0,
DADR7,DADR6,DADR5,DADR4,DADR3,DADR2,DADR1,DADR0;
 
output DOA31,DOA30,DOA29,DOA28,DOA27,DOA26,DOA25,DOA24,DOA23,DOA22,DOA21,DOA20,DOA19,DOA18,DOA17,DOA16,DOA15,DOA14,DOA13,DOA12,DOA11,DOA10,DOA9,DOA8,DOA7,DOA6,DOA5,DOA4,DOA3,DOA2,DOA1,DOA0,
DOB31,DOB30,DOB29,DOB28,DOB27,DOB26,DOB25,DOB24,DOB23,DOB22,DOB21,DOB20,DOB19,DOB18,DOB17,DOB16,DOB15,DOB14,DOB13,DOB12,DOB11,DOB10,DOB9,DOB8,DOB7,DOB6,DOB5,DOB4,DOB3,DOB2,DOB1,DOB0,
DOC31,DOC30,DOC29,DOC28,DOC27,DOC26,DOC25,DOC24,DOC23,DOC22,DOC21,DOC20,DOC19,DOC18,DOC17,DOC16,DOC15,DOC14,DOC13,DOC12,DOC11,DOC10,DOC9,DOC8,DOC7,DOC6,DOC5,DOC4,DOC3,DOC2,DOC1,DOC0;

/* module Mrf_ram (rfwrdata, rf_we_r, r_rdpm,
	rf_src1, rs1_dec_phys, rf_src2, rs2_dec_phys,
	rf_src3, rs3_phys_e, ss_clock);

input [31:0] rfwrdata;
input rf_we_r;
input [7:0] r_rdpm;
output [31:0] rf_src1;
input [7:0] rs1_dec_phys;
output [31:0] rf_src2;
input [7:0] rs2_dec_phys;
output [31:0] rf_src3;
input [7:0] rs3_phys_e;
input ss_clock;
*/

wire [31:0] rfwrdata = {DID31,DID30,DID29,DID28,DID27,DID26,DID25,DID24,DID23,DID22,
                        DID21,DID20,DID19,DID18,DID17,DID16,DID15,DID14,DID13,DID12,
                        DID11,DID10,DID9,DID8,DID7,DID6,DID5,DID4,DID3,DID2,DID1,DID0};
wire        rf_we_r  = {WED};
wire [7:0]  r_rdpm   = {DADR7,DADR6,DADR5,DADR4,DADR3,DADR2,DADR1,DADR0};
wire [7:0] rs1_dec_phys = {AADR7,AADR6,AADR5,AADR4,AADR3,AADR2,AADR1,AADR0};
wire [7:0] rs2_dec_phys = {BADR7,BADR6,BADR5,BADR4,BADR3,BADR2,BADR1,BADR0};
wire [7:0] rs3_phys_e   = {CADR7,CADR6,CADR5,CADR4,CADR3,CADR2,CADR1,CADR0};

wire [31:0] rf_src1;  
assign  {DOA31,DOA30,DOA29,DOA28,DOA27,DOA26,DOA25,DOA24,DOA23,DOA22,DOA21,DOA20,DOA19,DOA18,DOA17,DOA16,DOA15,DOA14,DOA13,DOA12,DOA11,DOA10,DOA9,DOA8,DOA7,DOA6,DOA5,DOA4,DOA3,DOA2,DOA1,DOA0} = rf_src1;

wire [31:0] rf_src2;
assign {DOB31,DOB30,DOB29,DOB28,DOB27,DOB26,DOB25,DOB24,DOB23,DOB22,DOB21,DOB20,DOB19,DOB18,DOB17,DOB16,DOB15,DOB14,DOB13,DOB12,DOB11,DOB10,DOB9,DOB8,DOB7,DOB6,DOB5,DOB4,DOB3,DOB2,DOB1,DOB0} = rf_src2;

wire [31:0] rf_src3;
assign {DOC31,DOC30,DOC29,DOC28,DOC27,DOC26,DOC25,DOC24,DOC23,DOC22,DOC21,DOC20,DOC19,DOC18,DOC17,DOC16,DOC15,DOC14,DOC13,DOC12,DOC11,DOC10,DOC9,DOC8,DOC7,DOC6,DOC5,DOC4,DOC3,DOC2,DOC1,DOC0} = rf_src3;


	reg [31:0] memory_array [135:0];		// DATA

	// RF write
	// model write as a master latch, so that write enable
	// can be de-asserted to prevent write

	always @ (posedge (rf_we_r)) begin
		#1
		if (rf_we_r===1) begin
			memory_array[r_rdpm] = rfwrdata;
		end
		else if(rf_we_r===1'bx) begin
			memory_array[r_rdpm] = 32'hx;
			if(~`SS_SCOPE.reset_iu && ( $time > 15 ))
			$display("*** X on rf_we_r - register file trashed");
		end
	end

	// read ports

	assign rf_src1 = rs1_dec_phys == 8'h00 ? 0 :
		((rs1_dec_phys===1'bx) | (rs1_dec_phys===r_rdpm)) ?
		32'bx : memory_array[rs1_dec_phys];
	assign rf_src2 = rs2_dec_phys == 8'h00 ? 0 :
		((rs2_dec_phys===1'bx) | (rs2_dec_phys===r_rdpm)) ?
		32'bx : memory_array[rs2_dec_phys];
	assign rf_src3 = rs3_phys_e == 8'h00 ? 0 :
		((rs3_phys_e===1'bx) | (rs3_phys_e===r_rdpm)) ?
		32'bx : memory_array[rs3_phys_e];


//-----------------------------------------------------------------------------
endmodule