/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)regfile.v 1.22 4/15/93
//-----------------------------------------------------------------------------
// REGISTER FILE, SPECIFIER PIPELINES, WINDOW TRANSLATION, and BYPASS
// COMPARATORS FOR B3 and B2
module Mregfile
(src1m, src2m, src3,
result, ld_iu, wr_lddatam_l,
rf_we_w,
nr_rdp,
nbrs1_decm, nbrs2_decm, brs3_d,
ncwpm_,
byp_rf3, byp_wr3, byp_res3,
hld_dirreg,
alus1_b3m, alus2_b3m,
word_store_d, half_store_d, byte_store_d,
hold, ss_clock, ss_scan_mode,
scan_in_mreg, scan_out_mreg
);
// REGISTER FILE PORTS -- 3 READ, 1 WRITE
output [31:0] src1m
; // register file read port 1 -- master latched
output [31:0] src2m
; // register file read port 2 -- master latched
output [31:0] src3
; // Register file read port 3
// WRITE DATA SOURCES
input [31:0] result
; // data from ALU for writing into rf
input [31:0] ld_iu
; // register file load data
input wr_lddatam_l
;
// WRITE ENABLE
input rf_we_w
; // register file write enable
// RESULT-STAGE RD ADDRESS PHYSICAL
input [7:0] nr_rdp
;
// REGISTER SPECIFIERS FROM INSTRUCTION IN DECODE
input [4:0] nbrs1_decm
; // source 1. reg. specifier in decode cycle buffered.
input [4:0] nbrs2_decm
; // source 2. reg. specifier in decode cycle buffered.
input [7:0] brs3_d
;
// CWP INPUTS FOR TRANSLATION
input [2:0] ncwpm_
; // cwp for read specifier translation (active low)
input byp_rf3
;
input byp_wr3
;
input byp_res3
;
input hld_dirreg
;
input alus1_b3m
; // bypass 3 to src 1
input alus2_b3m
; // bypass 3 to src 2
input word_store_d
;
input half_store_d
;
input byte_store_d
;
input hold
;
input ss_clock
;
input ss_scan_mode
;
input scan_in_mreg
;
output scan_out_mreg
;
// CLOCKS AND HOLD SIGNALS
//input ss_clock, hold;
//input scan_mode;
// forward declaration of registers
wire [31:0] rfwrdata
;
wire [7:0] r_rdpm
;
wire [2:0] cwpm_
;
wire [4:0] brs1_decm
;
wire [4:0] brs2_decm
;
wire [7:0] rs3_phys_e
;
wire word_store_e
;
wire half_store_e
;
wire byte_store_e
;
wire rf_we_r_almost
;
//---------------------------------------------------------------------------
// WRITE SPECIFIER PIPELINE
// write data
wire [31:0] nrfwrdata
;
// Expanded macro begin.
// cmux2(nrfwrdata_mux, 32, nrfwrdata, ld_iu, result, wr_lddatam_l)
function [32:1] nrfwrdata_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
nrfwrdata_mux = out_fn ;
end
endfunction
assign nrfwrdata = nrfwrdata_mux(ld_iu, result, wr_lddatam_l) ;
// Expanded macro end.
// this mux for scan only
wire [31:0] nrfwrdata_in
;
wire [31:0] nrfwrdata_scan
= {r_rdpm[0], rfwrdata[31:1]};
// Expanded macro begin.
// cmux2(nrfwrd_scan_mux, 32, nrfwrdata_in, nrfwrdata, nrfwrdata_scan, ss_scan_mode)
function [32:1] nrfwrd_scan_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
nrfwrd_scan_mux = out_fn ;
end
endfunction
assign nrfwrdata_in = nrfwrd_scan_mux(nrfwrdata, nrfwrdata_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_32 rfwrdata_reg_32(rfwrdata,nrfwrdata_in,ss_clock, (hold & ~ss_scan_mode)) ;
// Write address
// this mux for scan only
wire [7:0] nr_rdp_in
;
wire [7:0] nr_rdp_scan
=
{scan_in_mreg, r_rdpm[7:2], rf_we_r_almost};
// Expanded macro begin.
// cmux2(rrdpm_scan_mux, 8, nr_rdp_in, nr_rdp, nr_rdp_scan, ss_scan_mode)
function [8:1] rrdpm_scan_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
rrdpm_scan_mux = out_fn ;
end
endfunction
assign nr_rdp_in = rrdpm_scan_mux(nr_rdp, nr_rdp_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_8 r_rdpm_reg_8(r_rdpm,nr_rdp_in,ss_clock,(hold & ~ss_scan_mode)) ;
//------------------------------------------------------------
// register cwp
// this mux for scan only
wire [2:0] ncwpm_in
;
wire [2:0] ncwpm_scan
= {brs2_decm[1],cwpm_[2:1]};
// Expanded macro begin.
// cmux2(ncwpm_scan_mux, 3, ncwpm_in, ncwpm_, ncwpm_scan, ss_scan_mode)
function [3:1] ncwpm_scan_mux ;
input [3:1] in0_fn ;
input [3:1] in1_fn ;
input select_fn ;
reg [3:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
ncwpm_scan_mux = out_fn ;
end
endfunction
assign ncwpm_in = ncwpm_scan_mux(ncwpm_, ncwpm_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_3 cwpm__reg_3(cwpm_,ncwpm_in,ss_clock,(hold & ~ss_scan_mode)) ;
//---------------------------------------------------------------------------
// READ PORT 1 PIPELINE
// this mux for scan only
wire [4:0] nbrs1_decm_in
;
wire [4:0] nbrs1_decm_scan
= {cwpm_[0],brs1_decm[4:1]};
// Expanded macro begin.
// cmux2(nbrs1_decm_scan_mux, 5, nbrs1_decm_in, nbrs1_decm, nbrs1_decm_scan, ss_scan_mode)
function [5:1] nbrs1_decm_scan_mux ;
input [5:1] in0_fn ;
input [5:1] in1_fn ;
input select_fn ;
reg [5:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
nbrs1_decm_scan_mux = out_fn ;
end
endfunction
assign nbrs1_decm_in = nbrs1_decm_scan_mux(nbrs1_decm, nbrs1_decm_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_5 brs1_decm_reg_5(brs1_decm,nbrs1_decm_in,ss_clock, (hld_dirreg & ~ss_scan_mode)) ;
// rs1_specifier of next instruction into decode
wire [4:0] rs1_fetchm
= brs1_decm;
// address translation - rs1 physical address
wire [7:0] rs1_dec_phys
;
Mrf_xlate rs1_xlate(rs1_dec_phys, rs1_fetchm, cwpm_);
//---------------------------------------------------------------------------
// READ PORT 2 PIPELINE
// this mux for scan only
wire [4:0] nbrs2_decm_in
;
wire [4:0] nbrs2_decm_scan
=
{rs3_phys_e[1],brs2_decm[4:2],brs1_decm[0]};
// Expanded macro begin.
// cmux2(nbrs2_decm_scan_mux, 5, nbrs2_decm_in, nbrs2_decm, nbrs2_decm_scan, ss_scan_mode)
function [5:1] nbrs2_decm_scan_mux ;
input [5:1] in0_fn ;
input [5:1] in1_fn ;
input select_fn ;
reg [5:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
nbrs2_decm_scan_mux = out_fn ;
end
endfunction
assign nbrs2_decm_in = nbrs2_decm_scan_mux(nbrs2_decm, nbrs2_decm_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_5 brs2_decm_reg_5(brs2_decm,nbrs2_decm_in,ss_clock, (hld_dirreg & ~ss_scan_mode)) ;
// rs2 specifier from next instruction into decode
wire [4:0] rs2_fetchm
= brs2_decm;
// address translation - rs2 physical address
wire [7:0] rs2_dec_phys
;
Mrf_xlate rs2_xlate(rs2_dec_phys, rs2_fetchm, cwpm_);
//------------------------------------------------------------
// READ PORT 3
// this mux for scan only
wire [7:0] brs3_d_in
;
wire [7:0] brs3_d_scan
=
{r_rdpm[1],rs3_phys_e[7:2],brs2_decm[0]};
// Expanded macro begin.
// cmux2(brs3_d_scan_mux, 8, brs3_d_in, brs3_d, brs3_d_scan, ss_scan_mode)
function [8:1] brs3_d_scan_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
brs3_d_scan_mux = out_fn ;
end
endfunction
assign brs3_d_in = brs3_d_scan_mux(brs3_d, brs3_d_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_8 rs3_phys_reg_8(rs3_phys_e,brs3_d_in,ss_clock, (hold & ~ss_scan_mode)) ;
// this mux for scan only
wire word_store_d_in
;
wire word_store_d_scan
= byte_store_e;
// Expanded macro begin.
// cmux2(word_store_d_scan_mux, 1, word_store_d_in, word_store_d, word_store_d_scan, ss_scan_mode)
function [1:1] word_store_d_scan_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
word_store_d_scan_mux = out_fn ;
end
endfunction
assign word_store_d_in = word_store_d_scan_mux(word_store_d, word_store_d_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_1 word_st_e_reg_1(word_store_e,word_store_d_in,ss_clock, (hold & ~ss_scan_mode)) ;
// this mux for scan only
wire half_store_d_in
;
wire half_store_d_scan
= word_store_e;
// Expanded macro begin.
// cmux2(half_store_d_scan_mux, 1, half_store_d_in, half_store_d, half_store_d_scan, ss_scan_mode)
function [1:1] half_store_d_scan_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
half_store_d_scan_mux = out_fn ;
end
endfunction
assign half_store_d_in = half_store_d_scan_mux(half_store_d, half_store_d_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_1 half_st_e_reg_1(half_store_e,half_store_d_in,ss_clock, (hold & ~ss_scan_mode)) ;
// this mux for scan only
wire byte_store_d_in
;
wire byte_store_d_scan
= rs3_phys_e[0];
// Expanded macro begin.
// cmux2(byte_store_d_scan_mux, 1, byte_store_d_in, byte_store_d, byte_store_d_scan, ss_scan_mode)
function [1:1] byte_store_d_scan_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
byte_store_d_scan_mux = out_fn ;
end
endfunction
assign byte_store_d_in = byte_store_d_scan_mux(byte_store_d, byte_store_d_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_1 byte_st_e_reg_1(byte_store_e,byte_store_d_in,ss_clock, (hold & ~ss_scan_mode)) ;
// REGISTER FILE
// this mux for scan only
wire rf_we_w_in
;
wire rf_we_w_scan
= half_store_e;
// Expanded macro begin.
// cmux2(rf_we_w_scan_mux, 1, rf_we_w_in, rf_we_w, rf_we_w_scan, ss_scan_mode)
function [1:1] rf_we_w_scan_mux ;
input [1:1] in0_fn ;
input [1:1] in1_fn ;
input select_fn ;
reg [1:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
rf_we_w_scan_mux = out_fn ;
end
endfunction
assign rf_we_w_in = rf_we_w_scan_mux(rf_we_w, rf_we_w_scan, ss_scan_mode) ;
// Expanded macro end.
Mflipflop_1 rfwer_reg_1(rf_we_r_almost,rf_we_w_in,ss_clock, (hold & ~ss_scan_mode)) ;
wire rf_we_r
= rf_we_r_almost & ~ss_scan_mode;
wire [31:0] hp_rf_src1
, hp_rf_src2
, hp_rf_src3
;
//Mrf_ram rf_ram(rfwrdata, rf_we_r, r_rdpm,
// rf_src1, rs1_dec_phys, rf_src2, rs2_dec_phys,
// rf_src3, rs3_phys_e, ss_clock);
/***********Added logic to be able to use reg*****/
reg rf_src1_0
;
reg rf_src2_0
;
reg rf_src3_0
;
always @(rs1_dec_phys or rs2_dec_phys or rs3_phys_e)
begin
if (rs1_dec_phys == 0)
rf_src1_0 = 1'b1;
else
rf_src1_0 = 1'b0;
if (rs2_dec_phys == 0)
rf_src2_0 = 1'b1;
else
rf_src2_0 = 1'b0;
if (rs3_phys_e == 0)
rf_src3_0 = 1'b1;
else
rf_src3_0 = 1'b0;
end
reg rf_we_r_p
;
always @(ss_clock) begin
rf_we_r_p = rf_we_r & ~ss_clock;
end
/************ Register file called *******************/
HP136X32 rf_ram(
.DOA31(hp_rf_src1[31]),
.DOA30(hp_rf_src1[30]),
.DOA29(hp_rf_src1[29]),
.DOA28(hp_rf_src1[28]),
.DOA27(hp_rf_src1[27]),
.DOA26(hp_rf_src1[26]),
.DOA25(hp_rf_src1[25]),
.DOA24(hp_rf_src1[24]),
.DOA23(hp_rf_src1[23]),
.DOA22(hp_rf_src1[22]),
.DOA21(hp_rf_src1[21]),
.DOA20(hp_rf_src1[20]),
.DOA19(hp_rf_src1[19]),
.DOA18(hp_rf_src1[18]),
.DOA17(hp_rf_src1[17]),
.DOA16(hp_rf_src1[16]),
.DOA15(hp_rf_src1[15]),
.DOA14(hp_rf_src1[14]),
.DOA13(hp_rf_src1[13]),
.DOA12(hp_rf_src1[12]),
.DOA11(hp_rf_src1[11]),
.DOA10(hp_rf_src1[10]),
.DOA9(hp_rf_src1[9]),
.DOA8(hp_rf_src1[8]),
.DOA7(hp_rf_src1[7]),
.DOA6(hp_rf_src1[6]),
.DOA5(hp_rf_src1[5]),
.DOA4(hp_rf_src1[4]),
.DOA3(hp_rf_src1[3]),
.DOA2(hp_rf_src1[2]),
.DOA1(hp_rf_src1[1]),
.DOA0(hp_rf_src1[0]),
//
.DOB31(hp_rf_src2[31]),
.DOB30(hp_rf_src2[30]),
.DOB29(hp_rf_src2[29]),
.DOB28(hp_rf_src2[28]),
.DOB27(hp_rf_src2[27]),
.DOB26(hp_rf_src2[26]),
.DOB25(hp_rf_src2[25]),
.DOB24(hp_rf_src2[24]),
.DOB23(hp_rf_src2[23]),
.DOB22(hp_rf_src2[22]),
.DOB21(hp_rf_src2[21]),
.DOB20(hp_rf_src2[20]),
.DOB19(hp_rf_src2[19]),
.DOB18(hp_rf_src2[18]),
.DOB17(hp_rf_src2[17]),
.DOB16(hp_rf_src2[16]),
.DOB15(hp_rf_src2[15]),
.DOB14(hp_rf_src2[14]),
.DOB13(hp_rf_src2[13]),
.DOB12(hp_rf_src2[12]),
.DOB11(hp_rf_src2[11]),
.DOB10(hp_rf_src2[10]),
.DOB9(hp_rf_src2[9]),
.DOB8(hp_rf_src2[8]),
.DOB7(hp_rf_src2[7]),
.DOB6(hp_rf_src2[6]),
.DOB5(hp_rf_src2[5]),
.DOB4(hp_rf_src2[4]),
.DOB3(hp_rf_src2[3]),
.DOB2(hp_rf_src2[2]),
.DOB1(hp_rf_src2[1]),
.DOB0(hp_rf_src2[0]),
//
.DOC31(hp_rf_src3[31]),
.DOC30(hp_rf_src3[30]),
.DOC29(hp_rf_src3[29]),
.DOC28(hp_rf_src3[28]),
.DOC27(hp_rf_src3[27]),
.DOC26(hp_rf_src3[26]),
.DOC25(hp_rf_src3[25]),
.DOC24(hp_rf_src3[24]),
.DOC23(hp_rf_src3[23]),
.DOC22(hp_rf_src3[22]),
.DOC21(hp_rf_src3[21]),
.DOC20(hp_rf_src3[20]),
.DOC19(hp_rf_src3[19]),
.DOC18(hp_rf_src3[18]),
.DOC17(hp_rf_src3[17]),
.DOC16(hp_rf_src3[16]),
.DOC15(hp_rf_src3[15]),
.DOC14(hp_rf_src3[14]),
.DOC13(hp_rf_src3[13]),
.DOC12(hp_rf_src3[12]),
.DOC11(hp_rf_src3[11]),
.DOC10(hp_rf_src3[10]),
.DOC9(hp_rf_src3[9]),
.DOC8(hp_rf_src3[8]),
.DOC7(hp_rf_src3[7]),
.DOC6(hp_rf_src3[6]),
.DOC5(hp_rf_src3[5]),
.DOC4(hp_rf_src3[4]),
.DOC3(hp_rf_src3[3]),
.DOC2(hp_rf_src3[2]),
.DOC1(hp_rf_src3[1]),
.DOC0(hp_rf_src3[0]),
//
.WED(rf_we_r_p),
.OEA(1'b1),
.OEB(1'b1),
.OEC(1'b1),
//
.DID31(rfwrdata[31]),
.DID30(rfwrdata[30]),
.DID29(rfwrdata[29]),
.DID28(rfwrdata[28]),
.DID27(rfwrdata[27]),
.DID26(rfwrdata[26]),
.DID25(rfwrdata[25]),
.DID24(rfwrdata[24]),
.DID23(rfwrdata[23]),
.DID22(rfwrdata[22]),
.DID21(rfwrdata[21]),
.DID20(rfwrdata[20]),
.DID19(rfwrdata[19]),
.DID18(rfwrdata[18]),
.DID17(rfwrdata[17]),
.DID16(rfwrdata[16]),
.DID15(rfwrdata[15]),
.DID14(rfwrdata[14]),
.DID13(rfwrdata[13]),
.DID12(rfwrdata[12]),
.DID11(rfwrdata[11]),
.DID10(rfwrdata[10]),
.DID9(rfwrdata[9]),
.DID8(rfwrdata[8]),
.DID7(rfwrdata[7]),
.DID6(rfwrdata[6]),
.DID5(rfwrdata[5]),
.DID4(rfwrdata[4]),
.DID3(rfwrdata[3]),
.DID2(rfwrdata[2]),
.DID1(rfwrdata[1]),
.DID0(rfwrdata[0]),
//
.AADR7(rs1_dec_phys[7]),
.AADR6(rs1_dec_phys[6]),
.AADR5(rs1_dec_phys[5]),
.AADR4(rs1_dec_phys[4]),
.AADR3(rs1_dec_phys[3]),
.AADR2(rs1_dec_phys[2]),
.AADR1(rs1_dec_phys[1]),
.AADR0(rs1_dec_phys[0]),
//
.BADR7(rs2_dec_phys[7]),
.BADR6(rs2_dec_phys[6]),
.BADR5(rs2_dec_phys[5]),
.BADR4(rs2_dec_phys[4]),
.BADR3(rs2_dec_phys[3]),
.BADR2(rs2_dec_phys[2]),
.BADR1(rs2_dec_phys[1]),
.BADR0(rs2_dec_phys[0]),
//
.CADR7(rs3_phys_e[7]),
.CADR6(rs3_phys_e[6]),
.CADR5(rs3_phys_e[5]),
.CADR4(rs3_phys_e[4]),
.CADR3(rs3_phys_e[3]),
.CADR2(rs3_phys_e[2]),
.CADR1(rs3_phys_e[1]),
.CADR0(rs3_phys_e[0]),
//
.DADR7(r_rdpm[7]),
.DADR6(r_rdpm[6]),
.DADR5(r_rdpm[5]),
.DADR4(r_rdpm[4]),
.DADR3(r_rdpm[3]),
.DADR2(r_rdpm[2]),
.DADR1(r_rdpm[1]),
.DADR0(r_rdpm[0])
);
wire [31:0] rf_src1
= rf_src1_0 ? 0 : hp_rf_src1;
wire [31:0] rf_src2
= rf_src2_0 ? 0 : hp_rf_src2;
wire [31:0] rf_src3
= rf_src3_0 ? 0 : hp_rf_src3;
/**********************************************************************/
// select rf data or the bypass
wire [31:0] src1
;
// Expanded macro begin.
// cmux2(rf_src1_mux, 32, src1, rf_src1, rfwrdata, alus1_b3m)
function [32:1] rf_src1_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
rf_src1_mux = out_fn ;
end
endfunction
assign src1 = rf_src1_mux(rf_src1, rfwrdata, alus1_b3m) ;
// Expanded macro end.
wire [31:0] src2
;
// Expanded macro begin.
// cmux2(rf_src2_mux, 32, src2, rf_src2, rfwrdata, alus2_b3m)
function [32:1] rf_src2_mux ;
input [32:1] in0_fn ;
input [32:1] in1_fn ;
input select_fn ;
reg [32:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
rf_src2_mux = out_fn ;
end
endfunction
assign src2 = rf_src2_mux(rf_src2, rfwrdata, alus2_b3m) ;
// Expanded macro end.
wire [31:0] src3_prealgn
;
// Expanded macro begin.
// cmux3dnm(rf_src3_mux, 32, src3_prealgn, rf_src3, byp_rf3, rfwrdata, byp_wr3, result, byp_res3)
function [32:1] rf_src3_mux ;
input [32:1] in0_fn ;
input s0_fn ;
input [32:1] in1_fn ;
input s1_fn ;
input [32:1] in2_fn ;
input s2_fn ;
reg [32:1] out_fn ;
begin
case ({ byp_res3, byp_wr3, byp_rf3}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
rf_src3_mux = out_fn ;
end
endfunction
assign src3_prealgn = rf_src3_mux( rf_src3, byp_rf3, rfwrdata, byp_wr3, result, byp_res3) ;
// Expanded macro end.
// really should be input to
// rfwrdata reg.
// STORE aligner
wire [7:0] st_pa_byte0
= src3_prealgn[31:24];
wire [7:0] st_pa_byte1
= src3_prealgn[23:16];
wire [7:0] st_pa_byte2
= src3_prealgn[15:8];
wire [7:0] st_pa_byte3
= src3_prealgn[7:0];
wire [7:0] st_byte0
;
// Expanded macro begin.
// cmux3dnm(st_byte0_mux, 8, st_byte0, st_pa_byte0, word_store_e, st_pa_byte2, half_store_e, st_pa_byte3, byte_store_e)
function [8:1] st_byte0_mux ;
input [8:1] in0_fn ;
input s0_fn ;
input [8:1] in1_fn ;
input s1_fn ;
input [8:1] in2_fn ;
input s2_fn ;
reg [8:1] out_fn ;
begin
case ({ byte_store_e, half_store_e, word_store_e}) /* synopsys parallel_case */
3'b001: out_fn = in0_fn;
3'b010: out_fn = in1_fn;
3'b100: out_fn = in2_fn;
default: out_fn = 65'hx;
endcase
st_byte0_mux = out_fn ;
end
endfunction
assign st_byte0 = st_byte0_mux( st_pa_byte0, word_store_e, st_pa_byte2, half_store_e, st_pa_byte3, byte_store_e) ;
// Expanded macro end.
wire [7:0] st_byte1
;
// Expanded macro begin.
// cmux2(st_byte1_mux, 8, st_byte1, st_pa_byte3, st_pa_byte1, word_store_e)
function [8:1] st_byte1_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
st_byte1_mux = out_fn ;
end
endfunction
assign st_byte1 = st_byte1_mux(st_pa_byte3, st_pa_byte1, word_store_e) ;
// Expanded macro end.
wire [7:0] st_byte2
;
// Expanded macro begin.
// cmux2(st_byte2_mux, 8, st_byte2, st_pa_byte2, st_pa_byte3, byte_store_e)
function [8:1] st_byte2_mux ;
input [8:1] in0_fn ;
input [8:1] in1_fn ;
input select_fn ;
reg [8:1] out_fn ;
begin
case (select_fn) /* synopsys parallel_case */
1'b0: out_fn = in0_fn ;
1'b1: out_fn = in1_fn ;
default: out_fn = 65'hx;
endcase
st_byte2_mux = out_fn ;
end
endfunction
assign st_byte2 = st_byte2_mux(st_pa_byte2, st_pa_byte3, byte_store_e) ;
// Expanded macro end.
wire [7:0] st_byte3
= st_pa_byte3;
wire [31:0] src3 = {st_byte0, st_byte1, st_byte2, st_byte3};
wire [31:0] src1m = src1;
wire [31:0] src2m = src2;
wire scan_out_mreg = rfwrdata[0];
// synopsys translate_off
//---------------------------------------------------------------------------
// DISPLAY TASKS
task disp;
begin
$write("r_rdpm=%x (", r_rdpm);
Mtask.disp_laddr(Mtask.phy2log(r_rdpm)); $write(" ");
$write(") r_rdpm=%x (", r_rdpm);
Mtask.disp_laddr(Mtask.phy2log(r_rdpm));
$display(")");
$write("rs1_dec_phys=%x (", rs1_dec_phys);
Mtask.disp_laddr(Mtask.phy2log(rs1_dec_phys));
$display(")");
$write("rs2_dec_phys=%x (", rs2_dec_phys);
Mtask.disp_laddr(Mtask.phy2log(rs2_dec_phys));
$display(")");
$write("rfwrdata=%x ", rfwrdata);
// $write("next %x ", datam);
// if(wr_lddatam) $write("(LOAD DATA) ");
$display;
$display("src1m=%x src2m=%x", src1m, src2m);
$display("---------------------------------------------------------------------------");
#0 Mclocks.STOP = ~Mclocks.STOP;
end
endtask
//---------------------------------------------
// INITIALIZE REGISTER FILE TASK
task initrf;
input [31:0] testvalue;
integer ivar;
begin
for (ivar = 0; ivar < 136; ivar = ivar + 1)
begin
rf_ram.memory_array[ivar] = testvalue;
end
end
endtask
task initrf2;
input [31:0] testvalue;
integer ivar;
begin
for (ivar = 0; ivar < 136; ivar = ivar + 1)
begin
rf_ram.memory_array[ivar] = testvalue;
end
end
endtask
// synopsys translate_on
endmodule
// synopsys translate_off
This page: |
Created: | Thu Aug 19 12:00:33 1999 |
| From: |
../../../sparc_v8/ssparc/iu/Mregfile/rtl/regfile.v
|