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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)rl_pa_mux.v
***
****************************************************************************
****************************************************************************/
/********************************************************************************/
/* @(#)rl_pa_mux.v	1.17 3/27/93  */
/* rl_pa_mux.v*/
/**/
/*      Description:*/
/*              This module describes the physical address muxing*/
/*              (pa_mux) model.  This is a RTL model that describes*/
/*              the datapath of the multiplexing required to form*/
/*              the physical address from the tlb data and the*/
/*              virtual address.*/
/**/
/*      Dependencies:*/
/*              This module is instantiated by the mmu_dpath.v module.*/
/*              */
/**/
/********************************************************************************/

/* This module is broken down in 2 basic parts, registers and muxes.
 * The registers are CTPR, IBAR and PAR.  The muxing combines the
 * bypass virtual addresses, the mdata bus, the TLB data output (both
 * directly and Shifted), IBAR, CTPR and SSCR[30] bits.  The output
 * of the mux is the "data_pa" bus, which is registered in PAR to
 * hold the PA (physical address).  The "data_pa" is also driven
 * separately as the "dpa_out" bus, for the translated data cache address. */


module rl_pa_mux (bp_sel_30, bp_sel_28, bp_sel_21, bp_sel_20,
		bp_sel_19, bp_sel_18, bp_sel_17, bp_sel_16,
		bp_sel_15, bp_sel_14, bp_mux_sel0, 
		dpa_sel_b, dpa_sel_8d,
		ctpr_sel, dpa_sel_0,
		va_ptp8_sel, va_ptp4_sel, 
		io_range_sel, 
		sr_tw, io_tlb_tw,
                boot_mode, mmu_bypass, 
		tw_par, data_op,  
                io_op, io_mmu_bp, io_range,  
                tw_sm_lvl, 
		mdata_in05,
		tw_init_par,        /* CTPR/IBAR select */
		va_mux_sel_1, va_mux_sel_2,
		asi_dcd8_or_9, 
                ss_clock, ss_reset, ss_scan_mode);


output [1:0] bp_sel_30;        /* Bypass mux selects for bits [30:29].*/
output [1:0] bp_sel_28;        /* Bypass mux selects for bit [28].*/
output bp_sel_21;              /* Bypass mux selects for bits [27:21].*/
output [1:0] bp_sel_20;        /* Bypass mux selects for bit [20].*/
output [1:0] bp_sel_19;        /* Bypass mux selects for bit [19].*/
output [1:0] bp_sel_18;        /* Bypass mux selects for bit [18].*/
output [1:0] bp_sel_17;        /* Bypass mux selects for bit [17].*/
output [1:0] bp_sel_16;        /* Bypass mux selects for bit [16].*/
output [1:0] bp_sel_15;        /* Bypass mux selects for bit [15].*/
output [1:0] bp_sel_14;        /* Bypass mux selects for bit [14].*/
output bp_mux_sel0;            /* Bypass mux select for D0 */

output dpa_sel_b;              /* DPA mux select for ROOT/level-1 PTE*/
output dpa_sel_8d;             /* DPA mux selects for bits [09:08].*/
output ctpr_sel;               /* DPA mux selects for bits [07:04].*/
output dpa_sel_0;              /* DPA mux selects for bits [01:00].*/
output va_ptp8_sel;	
output [3:0] va_ptp4_sel;	

output [7:1] io_range_sel;

    input sr_tw;                 /* Bypass mux select for cpu_walk */
    input io_tlb_tw;             /* Bypass mux select for io_walk */
    input boot_mode;             /* reflects PCR boot mode indication bit*/
    input mmu_bypass;            /* MMU bypass decode (bypass = 1)*/
    input tw_par;                /* indicates tlb table walk in progress*/
    input data_op;               /* data translation request*/
    input io_op;                 /* IO translation/memory request*/
    input io_mmu_bp;             /* IO MMU bypass (bypass = 1).*/
    input [2:0] io_range;        /* reflects IOCP range field.*/
    input [1:0] tw_sm_lvl;       /* indicates level of current table walk*/

    input mdata_in05;            /* MSb of mdata_in.*/
    input tw_init_par;           /* CTPR/IBAR select */
    input va_mux_sel_1;          /* va_mux_sel[1] */
    input va_mux_sel_2;          /* va_mux_sel[2] */
    input asi_dcd8_or_9;         /* asi decode of 0x08 or 0x09  */

    input ss_clock;
    input ss_reset;
    input ss_scan_mode;

/*  */
/*************************************************************************/
/* PA mux select decodes.                                                */

    wire ctpr_sel = (sr_tw & tw_init_par);

/***** Bypass mux select decodes (bp_sel_xx) ****************************/
/*** Decode for ByPass_30 select 3,1 (4:1)   ****************************/

/***  data access asi 8 or 9 to instruction space                       ***/
/***  va_mux_sel_2 is va_mux_sel[2] from par_cntl                       ***/
/***  va_mux_sel_1 is va_mux_sel[1] from par_cntl                       ***/
/***  boot mode will turn bit 30,29,28 to 111 only on an instr. access  ***/
/***    or data access to asi_8 or 9 (instruction space) .a             ***/

    wire data_asi_8_9 = va_mux_sel_2 & asi_dcd8_or_9;
         
    assign bp_sel_30 = {(((boot_mode & (va_mux_sel_1 | data_asi_8_9)) |
			 (io_mmu_bp)) & ~ss_scan_mode),
                        (~(tw_par | io_mmu_bp |
			   (boot_mode & (va_mux_sel_1 | data_asi_8_9)))|
			   ss_scan_mode)};

/*** Decode for ByPass_28 select 3,1 (4:1)   */
	assign bp_sel_28 = {(boot_mode & (va_mux_sel_1 | data_asi_8_9) & 
			    ~ss_scan_mode),
                        (~((boot_mode & (va_mux_sel_1 | data_asi_8_9)) | tw_par)| 
                           ss_scan_mode)};

/*** Decode for ByPass_27_1 select 0  (3:1)   */
	assign bp_sel_21 = (~tw_par) | ss_scan_mode;

/* The next 8 bypass mux select require a decode of the io_range. */
/* Decode io_range input (3:8 decoder) */

	function [7:1] io_range_decode;

       input [2:0] io_range;

        case (io_range) // synopsys full_case parallel_case
		  3'b000:    io_range_decode = 7'b0000000;    /* IOCR range = 0*/
		  3'b001:    io_range_decode = 7'b0000001;    /* IOCR range = 1*/
		  3'b010:    io_range_decode = 7'b0000011;    /* IOCR range = 2*/
		  3'b011:    io_range_decode = 7'b0000111;    /* IOCR range = 3*/
		  3'b100:    io_range_decode = 7'b0001111;    /* IOCR range = 4*/
		  3'b101:    io_range_decode = 7'b0011111;    /* IOCR range = 5*/
		  3'b110:    io_range_decode = 7'b0111111;    /* IOCR range = 6*/
		  3'b111:    io_range_decode = 7'b1111111;    /* IOCR range = 7*/
/* synopsys translate_off */
          default:   io_range_decode = 7'bx;
/* synopsys translate_on */
      endcase
    endfunction

	wire [7:1] io_range_sel = io_range_decode(io_range);

/*** Decode for Bypass muxes - selects D0 input of bypass muxes */
    assign bp_mux_sel0 = ~(ctpr_sel | io_tlb_tw) | ss_scan_mode; 

/*** Decode for ByPass_20 select (4:1)   */
	wire [1:0] bp_sel_20 = {(io_tlb_tw & io_range_sel[7]),
                            (io_tlb_tw & ~io_range_sel[7])};

/*** Decode for ByPass_19 select (4:1)   */
	wire [1:0] bp_sel_19 = {(io_tlb_tw & io_range_sel[6]),
                            (io_tlb_tw & ~io_range_sel[6])};

/*** Decode for ByPass_18 select (4:1)   */
	wire [1:0] bp_sel_18 = {(io_tlb_tw & io_range_sel[5]),
                            (io_tlb_tw & ~io_range_sel[5])};

/*** Decode for ByPass_17 select (4:1)   */
	wire [1:0] bp_sel_17 = {(io_tlb_tw & io_range_sel[4]),
                            (io_tlb_tw & ~io_range_sel[4])};

/*** Decode for ByPass_16 select (4:1)   */
	wire [1:0] bp_sel_16 = {(io_tlb_tw & io_range_sel[3]),
                            (io_tlb_tw & ~io_range_sel[3])};

/*** Decode for ByPass_15 select (4:1)   */
	wire [1:0] bp_sel_15 = {(io_tlb_tw & io_range_sel[2]),
                            (io_tlb_tw & ~io_range_sel[2])};

/*** Decode for ByPass_14 select (4:1)   */
	wire [1:0] bp_sel_14 = {(io_tlb_tw & io_range_sel[1]),
                            (io_tlb_tw & ~io_range_sel[1])};


/***** Data Physical Address mux (2:1) select decode *********************/
/*** Decode for DPA base address [30:24] selects        */
/***     0 selects TLB data output.                     */
/***     1 selects the output of the Bypass address mux */
/** TIMING NOTE: dpa_sel_b should NOT be timing critical, all inputs should
 **              be stable at the beginning of the cycle.                   */

/*** DPA select for ROOT or LEVEL1 PTE*/

	wire dpa_sel_b = (io_tlb_tw | mmu_bypass | ctpr_sel) ;

/*** Decode for DPA mux (2:1) selects bits [11:10]       */
/***  dpa_sel_8d = 1 selects tb_out */

	assign dpa_sel_8d = ~(tw_par & ~(io_op | ctpr_sel |
                                  (~tw_sm_lvl[1] & tw_sm_lvl[0]))) ;

/*** Decode for DPA mux (3:1) selects bits [7:4], [3:2]       */
/*	this uses 'ctpr_sel'                                  */

/*** Decode for DPA mux (2:1) selects bits [1:0]              */

	wire dpa_sel_0 = (tw_par | ~(io_op | data_op));

/***** VA-mux Shift selects for PTP table walks (va_ptp_sel) ***************/
/* va_ptp8_sel decode from MMU_sm tablewalk level indication input signals */

    wire va_ptp8_sel = (sr_tw & ~tw_sm_lvl[1] & tw_sm_lvl[0]);  

/* va_ptp4_sel decode from MMU_sm tablewalk level indication input signals */
/* ss_scan_mode for mux control during scan, only va_ptp4_sel[0] on        */

	assign va_ptp4_sel = {(tw_par & ~ss_scan_mode & (io_op |
                           (~io_op & tw_sm_lvl[1] & tw_sm_lvl[0]))),  
                          (sr_tw & tw_sm_lvl[1] & ~tw_sm_lvl[0] & ~ss_scan_mode),
                          (sr_tw & ~tw_sm_lvl[1] & tw_sm_lvl[0] & ~ss_scan_mode),
                          (~tw_par | ss_scan_mode |
			   (~io_op & ~tw_sm_lvl[1] & ~tw_sm_lvl[0]))};


endmodule