/***     This file contains the PAR state machine and control logic.      ***/
/***     The PAR register is the single resource used in accessing both   ***/
/***     memory and I/O space. This state machine takes advantage of this ***/
/***     fact to control the translation sequencing and bus control       ***/
/***     for the MMU. Most of the other MMU logic is based on the         ***/
/***     current state of the PAR state machine.                          ***/
/***                                                                      ***/
/****************************************************************************/

rl_par_cntl  par_cntl(
		.par_sel (par_sel),	       // PAR select decode
		.req_pending (req_pending),    // Request pending in PAR
		.tlb_acc_cmp (tlb_acc_cmp),  // TLB ACC bits for compares
		.tlb_mbit_cmp (tlb_mbit_cmp),  // TLB mbit for compares
		.mbit_sel (mbit_sel),          // mbit mux select for TLB input
		.va_mux0_sel (va_mux0_sel),    // VA mux select for TLB input
		.va_mux1_sel (va_mux1_sel),    // VA mux selects for TLB input
		.va_mux_sel (va_mux_sel),      // VA mux selects 
		.ic_tlb (ic_tlb),	     // Par Control in IC_TLB state
		.ic_tlb_state (ic_tlb_state),// Par Control in IC_TLB state
		.ic_tlb_tw (ic_tlb_tw),	     // Par Control in IC_TLB_TW state
		.r_ic_par (r_ic_par),	     // Par Control in IC_TLB/PAR state
		.dc_tlb (dc_tlb),	     // Par Control in DC_TLB state
		.dc_tlb_state (dc_tlb_state),// Par Control in DC_TLB state
		.dc_tlb_tw (dc_tlb_tw),	     // Par Control in DC_TLB_TW state
		.wr_tlb_tw (wr_tlb_tw),	     // Par Control in WR_TLB_TW state
		.io_tlb (io_tlb),	     // Par Control in IO_TLB state
		.io_tlb_tw (io_tlb_tw),	     // Par Control in IO_TLB_TW state
		.wr_tlb (wr_tlb),	     // Par Control in WR_TLB state
		.r_dc_par (r_dc_par),	     // Par Control in DC_TLB/PAR state
		.r_sb_par (r_sb_par),	     // Par Control in IO_TLB state
                .sb_par (sb_par),            // output unregister sb_par to marb sm 
		.tw_par (tw_par),	     // Par Control in **_TLB_TW state
		.r_tw_par (r_tw_par),	     // Par Control in **_TLB_TW state
		.mmu_asi_op (mmu_asi_op),	
		.hold_par (hold_par),	     // Hold PAR register
		.ld_par (ld_par),	     // Load PAR register
		.io_tlb_nxt (io_tlb_nxt),    // I/O translation next cycle
		.data_op (data_op),          // D-cache translation this cycle
		.ic_in_par (ic_in_par),
		.dc_in_par (dc_in_par),
		.ic_par_state (ic_par_state),
		.dc_par_state (dc_par_state),
		.ipar_valid (hld_ipar),
		.dpar_valid (hld_dpar),
		.sr_tw (sr_tw),
		.r_pipe_moved (r_pipe_moved),
		.mm_mem_dbg (mm_mem_dbg),       // Memory access debug 

		.mm_dabort (mm_dabort),
		.mm_iabort (mm_iabort),
		.tlb_miss (tlb_miss),            // TLB miss this cycle
		.tlb_hit (tlb_hit),              // TLB hit this cycle
		.tlb_err (tlb_err),              // TLB error this cycle
		.tlb_m_miss (tlb_m_miss),        // Mbit miss this cycle
		.probe_done (probe_done),        // probe op done
		.asi_dcd3  (asi_dcd3),
		.asi_dcd3_w  (asi_dcd3_w),
		.ic_idle (ic_idle),              // signal to tell icache is idle
		.mem_issue_req (mem_issue_req),  // Memory request being issued
		.ic_miss (ic_miss),              // I$ tag miss
		.ic_miss_sustain (ic_miss_sustain),
		.dc_miss (dc_miss),              // D$ tag miss
		.dc_miss_sustain (dc_miss_sustain),
		.ldst_st (ldst_st),		  /* Store part of ldsto (D_ATOMIC) */
		.mbsy (mc_mbsy),                 // Memory busy signal
		.tw_done (tw_done),              // Table Walk done
		.flush_done (flush_done),        // flush op done
		.wb_valid_t (wb_valid_t),        // Write Buffer valid
		.wb_valid_x (wb_valid_x),        // Write Buffer valid
		.ldst_block (ldst_block),	  /* Store part of ldsto (D_ATOMIC) */
		.ld_op_e (ld_op_e),              // Load op in e-stage
		.st_op_e (st_op_e),              // Store op in e-stage
		.dvma_req_s (dvma_req_s),
		.dvma_req_x (dvma_req_x),
		.sbc_pa_valid (sbc_pa_valid),
		.st_op_w (st_op_w),             /* Store in W-stage */
		.last_st_w (last_st_w),         /* last Store in W-stage */
		.ldsto_w (ldsto_w),             /* ldst miss in W-stage */
		.read_w (read_w),               /* Load in W-stage */
		.r_cntl_space (r_cntl_space),   // Control space decode
		.mmasi (mmasi),
		.tw_abort  (tw_abort),
		.asi_done (asi_sm_done),
		.probe_in  (probe_in),
		.flush_in  (flush_in),
		.r_mbsy (r_mbsy),
		.r_mem_space (r_mem_space),
		.ic_issue_req (ic_issue_req),
		.dc_issue_req (dc_issue_req),
		.ld_par_tw (ld_par_tw),
		.normal_asi_w (normal_asi_w),
		.va_sel_par_in (va_sel_par_in),
		.iu_pipe_hold (iu_pipe_hold),
		.cam_reg_hld  (cam_reg_hld),
		.data_acc_s  (data_acc_s),
		.r_srd_ioreq (r_srd_ioreq),
		.sb_par_clr (sb_par_clr),
		.r_trap_w (r_trap_w),
		.pipe_moved (pipe_moved),
		.dcc_idle (dcc_idle),
		.wb_empty (wb_empty),
		.mreq_st (mm_mreq[3]),
		.ldtlb_tag_tw (ldtlb_tag_tw),
		.ic_stream (ic_stream),       /* Perfromance monitor decode */
		.dc_stream (dc_stream),       /* Perfromance monitor decode */
		.r_dc_miss (r_dc_miss),       /* Perfromance monitor decode */
		.flush_iopte (flush_iopte),
		.r_flush_entry (r_flush_entry),
		.tw_read_req (tw_read_req),
		.enbl_soft_tw (enbl_soft_tw),
		.st_miss_x (st_miss_x),
		.io_tlb_err (io_tlb_err),
		.mm_dstat_avail (mm_dstat_avail),
		.mm_cache_stat  (mm_cache_stat),  /* Cacheability status */
		.ss_clock (ss_clock),
		.ss_scan_mode (ss_scan_mode),
		.ss_reset (ss_reset));

/****************************************************************************/
/*** ASI (non-device space) decode logic                                  ***/
/***                                                                      ***/
/***     This file contains the decode logic for the current D-cache      ***/
/***     access. The ASI and virtual address are decoded to provide       ***/
/***     the appropriate control for the non-device space access.         ***/
/***                                                                      ***/
/****************************************************************************/

rl_asi_cntl  asi_cntl( .ic_asi  (ic_asi),
		.dc_asi  (dc_asi),
		.probe_in  (probe_in),
		.flush_in  (flush_in),
		.asi_dcd3  (asi_dcd3),
		.asi_dcd3_w  (asi_dcd3_w),
		.asi_dcd4  (asi_dcd4),
		.asi_dcd6  (asi_dcd6),
		.asi_dcd8_or_9  (asi_dcd8_or_9),
		.asi_dcd9  (asi_dcd9),
		.normal_asi_w  (normal_asi_w),
		.mmasi  (mmasi),
		.asi_write  (asi_write),
		.mmu_asi  (mmu_asi),
		.flush_tlb_pte  (flush_tlb_pte),
		.flush_tlb_seg  (flush_tlb_seg),
		.flush_tlb_reg  (flush_tlb_reg),
		.flush_tlb_ctx  (flush_tlb_ctx),
		.flush_tlb_all  (flush_tlb_all),
		.bypass_mmu_asi_w  (bypass_mmu_asi_w),
		.cntrl_spc_err  (cntrl_spc_err),
		.probe  (probe),
		.flush  (flush),
		.probe_entire  (probe_entire),
		.probe_lvl0  (probe_lvl0),
		.probe_lvl1  (probe_lvl1),
		.probe_lvl2  (probe_lvl2),
		.probe_lvl3  (probe_lvl3),
		.wb_3_asi  (wb_3_asi_buf),
		.wb_valid_x (wb_valid_x),    // Write Buffer valid
		.wb_valid_t (wb_valid_t),    // Write Buffer valid
		.wr_tlb (wr_tlb),
		.dc_miss_sustain (dc_miss_sustain),
		.asi_e  (iu_asi_e),
		.asi_w  (asi_w),
		.size_w  (size_w),
		.iu_size_e  (iu_size_e),
		.read_w  (read_w),
		.last_st_w  (last_st_w),
		.st_miss_x  (st_miss_x),
		.r_ldsto_w  (r_ldsto_w),
		.iu_dva  (r_d_vaddr[12:08]),
		.iu_pipe_hold  (iu_pipe_hold),
		.asi_done  (asi_done),
		.r_trap  (r_trap_w),
		.ok_2_probe  (ok_2_probe),
		.mmu_asi_op  (mmu_asi_op),
		.asidcd_mask  (asidcd_mask),
		.ss_clock  (ss_clock),
		.ss_scan_mode  (ss_scan_mode),
		.ss_reset  (ss_reset));

/****************************************************************************/
/*** MMU registers (non-datapath registers)                               ***/
/***                                                                      ***/
/***     This file contains the MMU control and status registers.         ***/
/***     The MMU error decode logic is also kept with the status          ***/
/***     registers. The address decode of the Control Space registers     ***/
/***     is also decoded here (as they are I/O control & status regs).    ***/
/***                                                                      ***/
/****************************************************************************/

rl_mmu_regs  mmu_regs(
	.enbl_br_fold (enbl_br_fold),     /* enable for branch folding  */
	.mm_fbpage_en (mm_fbpage_en),     /* enable for afx page hits   */
	.mm_page_hit_en (mm_page_hit_en), /* Decode of IO Control space regs */
	.mmu_cr  (mmu_cr),                /* MMU Control register output*/
	.io_range  (io_range),            /* IO Control register output*/
	.mmu_bypass  (mmu_bypass),        /* decode of mmu bypass cond.s*/
	.hld_ibar  (hld_ibar),            /* HOLD enable for IBAR */
	.tlb_addr  (tlb_addr),            /* TLB address (6-bits) */ 
	.hld_afar  (hld_afar),            /* AFAR hold enable */
	.hld_mfar  (hld_mfar),            /* MFAR hold enable */
	.afar_write  (afar_write),        /* Input mux select for AFAR*/
	.mfar_write  (mfar_write),        /* Input mux select for MFAR*/
	.sfar_write  (sfar_write),        /* Input mux select for SFAR*/
	.sfar_read  (sfar_read),          /* Input reset term for SFAR*/
	.dp_mux1_sel  (dp_mux1_sel),  
	.pamux_rd_sel  (pamux_rd_sel),
	.virt_ptp2  (virt_ptp2),
	.tlb_miss  (tlb_miss),            /* tlb_miss_raw gated w/ mmu_bypass*/
	.tlb_hit  (tlb_hit),              /* acc_ok gated w/ mmu_bypass*/
	.tlb_m_miss  (tlb_m_miss),        /* gated m_miss w/ mmu_bypass*/
	.tlb_err  (tlb_err),              /* gated tb_error w/ mmu_bypass*/
	.mm_dacc_err  (mm_dacc_err),      /* Data access err (parity error) */
	.mm_dacc_exc  (mm_dacc_exc),      /* Data access exception */
	.mm_dacc_miss  (mm_dacc_miss),    /* Data access MMU miss */
	.mm_dacc_wp  (mm_dacc_wp),        /* Data watchpoint trap */
	.wb_err  (wb_err),                /* Write buffer error   */
	.mm_cache_stat  (mm_cache_stat),  /* Cacheability status for caches */
	.mm_sb_err  (mm_sb_err),          /* Error occurred during IO DVMA */
	.mm_lvl15_int_l  (mm_lvl15_int_l),   /* Level 15 Interrupt */
	.mm_rfr_cntl  (mm_rfr_cntl),      /* DRAM Refresh Rate control */
	.mm_oddpar  (mm_oddpar),
	.mm_parity_en  (mm_parity_en),
	.mm_sbae  (mm_sbae),              /* Sbus Arb enable bits from MID */
        .mm_rom_module_speed  (mm_rom_module_speed),
	.hold_sfar  (hold_sfar),
	.boot_out_30  (boot_out_30),      /* PA[30] non datapath mux output */
	.io_mmu_bp  (io_mmu_bp),          /* IO Bypass mode */
	.probe_err  (probe_err),
	.r_tw_err  (r_tw_err),            /* Reg'd TableWalk err */
	.tw_err  (tw_err),                /* TableWalk err */
	.priv_err_x  (priv_err_x),        /* Privilege Error  */
	.prtct_err_x  (prtct_err_x),      /* Protection Error */
	.io_tlb_err  (io_tlb_err),
	.flush_iopte  (flush_iopte),      /* Flush IOPTE from TLB */
	.flush_ioall  (flush_ioall),      /* Flush all IOPTEs from TLB */
	.mm_bp_dtct  (mm_bp_dtct),        /* Break Point Detected      */
	.boot_mode  (boot_mode),          /* Boot Mode - Ifetch from EPROM */
// deleted 	.mmu_en_e  (mmu_en_e),
	.r_acc_err_tw  (r_acc_err_tw),
	.mm_sscr_ba8  (mm_sscr_ba8),
	.par_cbit  (par_cbit),
	.ipar_cbit  (ipar_cbit),
	.dpar_cbit  (dpar_cbit),
	.mop_c_bit  (mop_c_bit),
	.mop_mreq  (mop_mreq),
	.tw_perr  (tw_perr),
	.iacc_miss  (iacc_miss),
	.dacc_miss  (dacc_miss),
	.enbl_soft_tw  (enbl_soft_tw),
	.io_mmu_en  (io_mmu_en),
	.sup_nalloc  (sup_nalloc),
	.mm_fs_lvl (mm_fs_lvl),
	.mm_fs_perr (mm_fs_perr),
	.mm_fs_iae (mm_fs_iae),
	.mm_fs_xerr (mm_fs_xerr),
	.mm_fs_mmiss (mm_fs_mmiss),
	.mm_fs_sbe (mm_fs_sbe),
	.mm_fs_sto (mm_fs_sto),
	.mm_fs_sptct (mm_fs_sptct),
	.ld_pcntr_a (ld_pcntr_a),
	.ld_pcntr_b (ld_pcntr_b),
	.trig_a (trig_a),
	.trig_b (trig_b),
	.iva_wp_sel (iva_wp_sel),
	.sel_brkpt_mux (sel_brkpt_mux),
	.vaf_en_hld (vaf_en_hld),
	.va_bp_hld (va_bp_hld),
	.va_src_sel (va_src_sel),
	.mmu_brkpt_en (mmu_brkpt_en),
	.afx_qlvl (afx_qlvl),
	.r_mem_issue_req (r_mem_issue_req),
	.sbus_id_hit (sbus_id_hit),
	.r_tlb_compare (r_tlb_compare),
	.r_sup_mode (r_sup_mode),
	.mm_go_standby (mm_go_standby),	// Automatic programmable standby

/*** inputs ***/
	.turn_off_standby (turn_off_standby),	// turn off programmable standby
	.r_dc_par (r_dc_par),           /* D-cache address in PAR */
	.r_ic_par (r_ic_par),           /* I-cache address in PAR */
	.marb_busy (marb_busy),		/* Memory arb sm busy */
        .bm_sel (bm_sel),               // if set, boot from SBus, else AFX
	.cntrl_spc_err (cntrl_spc_err),
	.mm_dabort (mm_dabort),
	.normal_asi_w (normal_asi_w),
	.cam_reg_hld  (cam_reg_hld),
	.misc  (misc),
	.dvma_req_x  (dvma_req_x),
	.wb_valid_x  (wb_valid_x_reg),
	.st_miss_x  (st_miss_x_reg),
	.read_w  (read_w_reg),
	.ldd_w  (ldd_w),
	.misc_in  (misc_in),
	.mmdaten  (mmdaten),
	.mmu_daten  (mmdaten),
	.hld_mmu_cr  (hld_mmu_cr),
	.hld_sfsr  (hld_sfsr),
	.rd_sfsr  (rd_sfsr),
	.hld_trcr  (hld_trcr),
	.tw_trcr_hld  (tw_trcr_hld),
	.dp_perr  (dp_perr),
	.sb_err_type  (sb_err_type),
	.sb_wrt_err  (sb_wrt_err),
	.sb_errsize  (sb_errsize),
	.hold_par  (hold_par),
	.cbit_in  (cbit_in),
	.tlb_acc_raw  (tlb_acc_raw),
	.mmstben_reg  (mmstben_reg),
	.pipe_moved (pipe_moved),             /*         */
	.r_tlb_used (r_tlb_used),
	.r_mbsy (r_mbsy),                 /* write decode for MEMIF          */
	.mmstben_aarb  (mmstben_aarb),
	.mmreg_rd_asi  (mmreg_rd_asi),
	.mmreg_rd_cs  (mmreg_rd_cs),
	.bypass_mmu_asi  (bypass_mmu_asi),
	.asi_dcd3  (asi_dcd3),
	.asi_dcd4  (asi_dcd4),
	.asi_dcd6  (asi_dcd6),
	.r_dva_12_8  (r_d_vaddr[12:08]),
	.r_dva_7_2  (r_d_vaddr[07:02]),
	.mm_pa  (mm_pa),
	.cxr  (cxr), 
	.tlb_lvl  (tlb_lvl),
	.pa_mux_rd  (pa_mux_rd),
	.data_acc_s  (data_acc_s),
	.tw_par  (tw_par),
	.tlb_miss_raw  (tlb_miss_raw),
	.m_miss  (m_miss),
	.acc_ok  (acc_ok),
	.c_en  (c_en),
	.tw_write  (tw_write_req),
	.data_op  (data_op),
	.io_op  (io_op),
	.tw_addr_err  (tw_addr_err),
	.tw_xlat_err  (tw_xlat_err),
	.hld_sfar  (hld_sfar),
	.sb_sbslot  (sb_sbslot),
	.iu_pipe_hold  (iu_pipe_hold),
	.tw_err_lvl  (tw_err_lvl),
	.tlb_flush  (tlb_flush),
	.mem_issue_req  (mem_issue_req),
	.tw_init_par  (tw_init_par),
	.tw_prb_err  (tw_prb_err),
	.probe_invalid  (probe_invalid),
	.probe_done  (probe_done),
	.probe  (probe),
	.sb_ioa  (sb_ioa[31:24]),
	.io_range_sel  (io_range_sel),
	.sb_write  (sb_write),
	.r_srd_ioreq  (r_srd_ioreq),
	.r_sxlate_ioreq  (r_sxlate_ioreq),
	.sb_va_val_l  (sb_va_val_l),
	.ic_tlb  (ic_tlb),
	.ic_tlb_state (ic_tlb_state),
	.r_ic_tlb  (r_ic_tlb),
	.r_tlb_miss  (r_tlb_miss),
	.r_dc_tlb  (r_dc_tlb),
	.r_wr_tlb  (r_wr_tlb),
	.dc_tlb  (dc_tlb),
	.dc_tlb_state (dc_tlb_state),
	.wr_tlb  (wr_tlb),
	.r_mstb_l  (r_mstb_l),
	.mm_dccfstb  (mm_dccfstb),
	.mmulgc_bp_hit  (mmulgc_bp_hit),
	.iwait_state  (iwait_state),
	.mm_mreq  (mm_mreq),
	.io_issue_req  (io_issue_req),
	.io_tlb_tw  (io_tlb_tw),
	.root_tw  (root_tw),
	.pt1_tw  (pt1_tw),
	.pt2_tw  (pt2_tw),
	.tw_pte_chk  (tw_pte_chk),
	.dc_tlb_tw  (dc_tlb_tw),
	.wr_tlb_tw (wr_tlb_tw),
	.ic_tlb_tw  (ic_tlb_tw),
	.asi_dcd9_w  (asi_dcd9),
	.io_tw_wrt  (io_tw_wrt),
	.sr_tw_wrt  (sr_tw_wrt),
	.sb_cyc_pnd  (sb_cyc_pnd),
	.dmiss_for_m  (dmiss_for_m),
	.ipar_valid  (hld_ipar),
	.dpar_valid  (hld_dpar),
	.ic_par_state (ic_par_state),
	.dc_par_state (dc_par_state),
	.mm_dstat_avail (mm_dstat_avail),
	.mm_istat_avail (mm_istat_avail),
	.dc_in_par (dc_in_par),
	.r_dc_in_par (r_dc_in_par),
	.r_ic_in_par (r_ic_in_par),
	.r_sb_par (r_sb_par),
	.mmu_asi_op (mmu_asi_op),
	.r_ic_miss (r_ic_miss),
	.r_dc_miss (r_dc_miss),
	.dc_miss_sustain (dc_miss_sustain),
	.ic_miss_sustain (ic_miss_sustain),
	.iu_sfs_sup (iu_sfs_sup),
	.iu_sfs_perr (iu_sfs_perr),
	.iu_sfs_xerr (iu_sfs_xerr),
	.iu_sfs_mmiss (iu_sfs_mmiss),
	.iu_sfs_iae (iu_sfs_iae),
	.iu_sfs_sbe (iu_sfs_sbe),
	.iu_sfs_sto (iu_sfs_sto),
	.iu_sfs_prtct (iu_sfs_prtct),
	.iu_sfs_priv (iu_sfs_priv),
	.iu_sfs_lvl (iu_sfs_lvl),
	.iu_mm_iacc_wp_exc_d (iu_mm_iacc_wp_exc_d),
	.r_sb_ic_op (r_sb_ic_op),         /* Last PIO was for I-cache miss   */
	.tb_error (tb_error),
	.r_io_space (r_io_space),
	.r_cntl_space (r_cntl_space),
	.r_pci_space (r_pci_space),
	.mm_iabort (mm_iabort),
        .mm_cpsb_wrt (mm_cpsb_wrt),       /* indicates PIO write     */
	.pio_data_rcvd (pio_data_rcvd),	  /* PIO data received               */
	.r_drd_c1 (r_drd_c1),         /* Marb state DRD_C1 reg'd    */
	.dc_stream (dc_stream),       /* Perfromance monitor decode */
	.ic_stream (ic_stream),       /* Perfromance monitor decode */
	.ihold_d1 (ihold_d1),           // for MMU perf counter trigger
        .dhold_d1 (dhold_d1),           // for MMU perf counter trigger  
        .dc_shold (dc_shold),           // for MMU perf counter trigger  
        .did_ifetch (did_fetch),        // for MMU perf counter trigger
        .did_dfetch (dfetch),           // for MMU perf counter trigger
	.fhold_d1 (fhold_d1),
	.fhold_fqfull_d1 (fhold_fqfull_d1),
	.iu_sup_mode (iu_sup_mode),
        .mm_page (mm_page),             // for MMU perf counter trigger
        .sr_tw (sr_tw),		        // for MMU perf counter trigger
        .pcntr_a_co (pcntr_a_co),       // for MMU perf counter trigger
        .pcntr_b_co (pcntr_b_co),       // for MMU perf counter trigger
	.p_reply_dec (p_reply_dec),
	.r_p_reply_dec (r_p_reply_dec),
	.precharge_early_0 (precharge_early_0),
	.precharge_early_1 (precharge_early_1),
        .odd_wd (odd_wd),
	.sel_cache_stat (sel_cache_stat), /* MMU register select decode */
        .w_sp_sel (w_sp_sel),			// Speed select (for mmu status)
        .w_div_ctl (w_div_ctl),			// Divide by cntl (mmu status)
        .mc_afx_to (mc_afx_to),			// AFX timeout indicator 
	.afx_qbusy (afx_qbusy),
	.r_fb_space (r_fb_space),         /* AFX space decoded               */
	.ldtlb_data_tw (ldtlb_data_tw),   /* Loading TLB next cycle (tw)     */
	.iu_in_trap  (iu_in_trap),
	.hold_fetch_f_l  (hold_fetch_f_l),
	.ss_clock  (ss_clock),
	.ss_reset  (ss_reset),
	.ss_reset_any  (ss_reset_any),
	.ss_scan_mode  (ss_scan_mode));

rl_va_mux  va_muxl(
		.tlb_wrt_tag  (tlb_wrt_tag),
		.tlb_asel  (tlb_asel),
		.tlb_io_bit  (tlb_io_bit),
		.c_en  (c_en),
		.hld_mmu_cr  (hld_mmu_cr),
		.hld_ctpr  (hld_ctpr),
		.hld_sfsr  (hld_sfsr),
		.rd_sfsr  (rd_sfsr),
		.hld_sfar  (hld_sfar),
		.hld_trcr  (hld_trcr),
		.hld_cxr  (hld_cxr),
		.io_op  (io_op),
		.sel_mdat_mux  (sel_mdat_mux),
		.mmstben_reg  (mmstben_reg),
		.dp_asi_dcd6  (dp_asi_dcd6),
		.r_d_vaddr  (r_d_vaddr[12:08]),
		.r_d_vaddr_02  (r_d_vaddr[02]),
		.io_tlb_nxt  (io_tlb_nxt),
		.tw_io_bit  (tw_io_bit),
		.asi_write  (asi_write),
		.asi_dcd4  (asi_dcd4),
		.asi_dcd6  (asi_dcd6),
		.tlb_asi_act  (tlb_asi_act),
		.mmstben  (mmstben),
		.mmstben_aarb  (mmstben_aarb),
		.mmreg_rd_asi  (mmreg_rd_asi),
		.tlb_tag_we  (ldtlb_tag_tw),
		.mmu_asi_op (mmu_asi_op),	/* ASI op in par cntl sm */
		.tlb_data_we  (ldtlb_data_tw),
		.tlb_update  (tlb_update),
		.tlb_tag_reload  (tlb_cam_reload),
		.flush_iopte  (flush_iopte),
		.flush_ioall  (flush_ioall),
//  deleted	.mmu_en_e  (mmu_en_e),
					/* fix compare, swift bug found in mmu_cxtctp */
		.mmu_en_e  (mmu_en),	/* by using staged mmu_en not mmu_en_e */
		.tlb_flush  (tlb_flush),
		.io_mmu_en  (io_mmu_en),
		.ss_clock  (ss_clock),
		.ss_reset  (ss_reset));

rl_pa_mux pa_muxl(
		  .bp_sel_30 (bp_sel_30),
		  .bp_sel_28 (bp_sel_28),
		  .bp_sel_21 (bp_sel_21),
		  .bp_sel_20 (bp_sel_20),
		  .bp_sel_19 (bp_sel_19),
		  .bp_sel_18 (bp_sel_18),
		  .bp_sel_17 (bp_sel_17),
		  .bp_sel_16 (bp_sel_16),
		  .bp_sel_15 (bp_sel_15),
		  .bp_sel_14 (bp_sel_14),
		  .bp_mux_sel0 (bp_mux_sel0),
		  .dpa_sel_b (dpa_sel_b),
		  .dpa_sel_8d (dpa_sel_8d),
		  .ctpr_sel (ctpr_sel),
		  .dpa_sel_0 (dpa_sel_0),
		  .va_ptp8_sel (va_ptp8_sel),
		  .va_ptp4_sel (va_ptp4_sel),
		  .io_range_sel (io_range_sel),
		  .sr_tw (sr_tw),
		  .io_tlb_tw (io_tlb_tw),
		  .boot_mode (boot_mode),
		  .mmu_bypass (mmu_bypass),
		  .tw_par (tw_par),
		  .data_op (data_op),
		  .io_op (io_op),
		  .io_mmu_bp (io_mmu_bp),
		  .io_range (io_range),
		  .tw_sm_lvl (tw_sm_lvl),
		  .mdata_in05 (misc_in[05]),
		  .tw_init_par (tw_init_par),  /* CTPR/IBAR load select*/
		  .va_mux_sel_1 (va_mux_sel[0]),
                  .va_mux_sel_2 (va_mux_sel[1]),
		  .asi_dcd8_or_9 (asi_dcd8_or_9),
		  .ss_clock (ss_clock),
		  .ss_scan_mode (ss_scan_mode),
		  .ss_reset (ss_reset)
		  );


endmodule