/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)start_sm.v
***
***  Description:
***   This is afxmaster state machine generates the read start
***   flags that indicate that the dma read transaction 
***   may start on the afxmaster. It also generates the
***   'delayed_read' flag that indicates that a delayed
***   read is currently being performed by the afxmaster.
***
****************************************************************************
****************************************************************************/
`define START_IDLE  2'b00
`define START       2'b01
`define DEL_READ    2'b10

`timescale      1ns/1ns



module start_sm (read_start, delayed_read,
		pclk, reset_l, cmd_start, cmd_start1,
                pci_mem_rd, write_fifos_empty,
                tar_xmt_fifo_empty, force_pci_retry, idle_cyc,
		ack_quiescence);

    output read_start;   		// read_start flag
    output delayed_read;   		// delayed read flag
    input pclk;         		// pci clk
    input reset_l;      		// system or PCI reset_l
    input cmd_start;      		// pci cmd valid
    input cmd_start1;      		// delayed pci cmd valid
    input pci_mem_rd;      		// pci cmd is memory read
    input write_fifos_empty;      	// tar_rcv fifos empty
    input tar_xmt_fifo_empty;      	// tar_xmit (read) fifo empty
    input force_pci_retry;      	// read retry (delayed read)
    input idle_cyc;      		// afxm_sm idle cyc in pclk domain
					// retried address
    input ack_quiescence;      		// PCI in quiescent state


    wire  [1:0] start_state;		// curr state of retry sm

function [1:0] rd_start_sm;

    input  [1:0] start_state;
    input reset_l;      		// system or PCI reset_l
    input cmd_start;      		// pci cmd valid
    input cmd_start1;      		// delayed pci cmd valid
    input pci_mem_rd;      		// pci cmd is memory read
    input write_fifos_empty;      	// tar_rcv fifos empty
    input tar_xmt_fifo_empty;      	// tar_xmit (read) fifo empty
    input force_pci_retry;      	// read retry (delayed read)
    input idle_cyc;      		// afxm_sm idle cyc in pclk domain
    input ack_quiescence;      		// PCI in quiescent state

    reg  [1:0] start_ns;		// next_state


    begin
       if (~reset_l | ack_quiescence) begin
        start_ns = `START_IDLE;
       end 
       else begin 
        start_ns = start_state;
   	case (start_state)
	    `START_IDLE: begin
                  if (cmd_start & ~cmd_start1 &
                      pci_mem_rd & write_fifos_empty &
              	      tar_xmt_fifo_empty & ~force_pci_retry) 
                      start_ns = `START;  
                  else
                      start_ns = `START_IDLE;  
		  end
	    `START: begin
		  if (~idle_cyc)
                       start_ns = `DEL_READ;  
		  else
                       start_ns = `START;  
		end
	    `DEL_READ: begin
                  if (~tar_xmt_fifo_empty) 
                      start_ns = `START_IDLE;  
                  else 
                      start_ns = `DEL_READ;   
		end
	    default: begin
                      start_ns = `START_IDLE;   
		//synopsys translate_off
		if (reset_l) $display("start_sm:  Error!");
		//synopsys translate_on
	        end
   	endcase 
      end
      rd_start_sm = start_ns;
    end
endfunction

reg  [1:0] sm_output;
always @(posedge pclk) begin
    sm_output <= #1 rd_start_sm(start_state,
    			reset_l, cmd_start, cmd_start1, 
			pci_mem_rd, write_fifos_empty,
                        tar_xmt_fifo_empty, force_pci_retry, idle_cyc,
			ack_quiescence);
end

assign start_state = sm_output;

wire read_start = (start_state==`START);
wire delayed_read = (start_state==`START) || (start_state==`DEL_READ);



endmodule