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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)start_xfer_sm.v
***
***  Description:
***   This is afxmaster state machine generates the start_xfer
***   pulse that indicates the start of a DMA read or write
***   transaction.  Implementing this pulse generation via a
***   state machine makes it more immune to asynchronous
***   timing variations.  
***
****************************************************************************
****************************************************************************/
`define START_IDLE  2'b00
`define START_XFER  2'b01
`define WAIT_END    2'b10

`timescale      1ns/1ns



module start_xfer_sm (start_xfer, 
		clk, reset_l, cmd_start, cmd_start1,
                pci_mem_wrt, pci_mem_rd, retry_condition,
		write_fifos_empty, tar_xmt_fifo_empty , idle_cyc,
		force_pci_retry);

    output start_xfer;   		// start_xfer pulse signal to afxm
    input clk;	         		// pclk or gclk
    input reset_l;      		// system or PCI reset_l
    input cmd_start;      		// pci cmd valid
    input cmd_start1;      		// delayed pci cmd valid
    input pci_mem_wrt;      		// pci cmd is memory write
    input pci_mem_rd;      		// pci cmd is memory read
    input retry_condition;   		// retry signal to pci slave
    input write_fifos_empty;      	// tar_rcv fifos empty
    input tar_xmt_fifo_empty;      	// tar_xmit (read) fifo empty
    input idle_cyc;      		// afxm_sm idle cyc in clk domain
    input force_pci_retry;      	// delayed read retry


    wire  [1:0] start_state;		// curr state of retry sm

function [1:0] start_xfer_sm;

    input  [1:0] start_state;
    input reset_l;      		// system or PCI reset_l
    input cmd_start;      		// pci cmd valid
    input cmd_start1;      		// delayed pci cmd valid
    input pci_mem_wrt;      		// pci cmd is memory write
    input pci_mem_rd;      		// pci cmd is memory read
    input retry_condition;   		// retry signal to pci slave
    input write_fifos_empty;      	// tar_rcv fifos empty
    input tar_xmt_fifo_empty;      	// tar_xmit (read) fifo empty
    input idle_cyc;      		// afxm_sm idle cyc in clk domain
    input force_pci_retry;      	// delayed read retry

    reg  [1:0] start_ns;		// next_state


    begin
       if (~reset_l) begin
        start_ns = `START_IDLE;
       end 
       else begin 
        start_ns = start_state;
   	case (start_state)
	    `START_IDLE: begin
		//2.0: added ~cmd_start1 to read term to get 
		//     rid of spurious start_xfer pulse
                  if ((cmd_start1 & pci_mem_wrt & idle_cyc & write_fifos_empty) |
               	      (cmd_start & ~cmd_start1 & pci_mem_rd & write_fifos_empty & 
		       tar_xmt_fifo_empty & ~force_pci_retry)) 
                      start_ns = `START_XFER;  
                  else
                      start_ns = `START_IDLE;  
		end
	    `START_XFER: begin
                       start_ns = `WAIT_END;  
		end
	    `WAIT_END: begin
		       if (~cmd_start)
                          start_ns = `START_IDLE;  
		       else
                          start_ns = `WAIT_END;  
		end
	    default: begin
                      start_ns = `START_IDLE;   
		//synopsys translate_off
		if (reset_l) $display("start_xfer_sm:  Error!");
		//synopsys translate_on
	        end
   	endcase 
      end
      start_xfer_sm = start_ns;
    end
endfunction

reg  [1:0] sm_output;
always @(posedge clk) begin
    sm_output <= #1 start_xfer_sm(start_state,
    			reset_l, cmd_start, cmd_start1,
			pci_mem_wrt, pci_mem_rd, retry_condition,
			write_fifos_empty, tar_xmt_fifo_empty, idle_cyc,
			force_pci_retry);
end

assign start_state = sm_output;

wire start_xfer = (start_state==`START_XFER);



endmodule