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Xilinx Answer #2093 : XC7000: Device Slew Rates (Rise/Fall times)
Xilinx Answer #2079 : 7336 part programmed by BP Micro programmer works, but HW-130 programmed part does not--LOWPWR problem
Xilinx Answer #1842 : XC7336: Programming gives product ID error
Xilinx Answer #1801 : XC7300: MR (Master Reset) Pin can optionally be used as an input
Xilinx Answer #1712 : 7300: Fast clock driver is connected to non-fast clock pin
Xilinx Answer #1703 : XC7300: Can I use a product term Output Enable in a Fast Function Block (FFB)
Xilinx Answer #1453 : XC7336/XC7318: "Drive Unused IO Pads on Chip" option not available for 7336, 7318
Xilinx Answer #1442 : XEPLD 6.x: Unexpected error detected, please report to Xilinx with reference "epldinst.cc40."
Xilinx Answer #1439 : XC73144: How to configure programmable ground option
Xilinx Answer #1403 : XC9500/XC7000: Translate warning 295: The LOC parameter 'LOC=FB1_16' on the macro symbol $1I1 is not supported for XC7000 designs
Xilinx Answer #998 : XC7300F electrical characteristics
Xilinx Answer #868 : Differences between DS550 (EPLD) software versions 5.x and 6.0
Xilinx Answer #666 : 7336 or 7318 functions incorrectly after being programmed by Data I/O programmer
Xilinx Answer #622 : Programmers: XELTEK: SuperPro, SuperPro II has a bad XC7318/1736 algorithm (ver. 2.2)
Xilinx Answer #615 : Unbonded Fast Output Enable (FOE) can't be specified.
Xilinx Answer #568 : 94 DATA BOOK 3rd: page 3-64, pinout error for 73144PQ160
Xilinx Answer #472 : Differences between the 7318/7336 and 7354/7372/73108/73144
Xilinx Answer #460 : Slow VCC rise time does not require use of /MR as a 'hold-off'
Xilinx Answer #459 : Use of /MR as input precludes use as reset, even during initialization
Xilinx Answer #450 : 94 DATA BOOK 2nd: Which 7300 outputs have 24mA drive capability?
Xilinx Answer #432 : How flip-flop initial states are determined
Xilinx Answer #367 : XACT 5: Acessing fast input pins for High Density Function Blocks
Xilinx Answer #362 : What is the fastest pin to pin delay?
Xilinx Answer #259 : 94 DATA BOOK has incorrect pinout for 73108 EPLD pin 160
Xilinx Answer #237 : Programming XC7000 part with a JEDEC file gives checksum error